The exhaustive changes of the hardware con-
text in configurable computing machines increase
the risk of configuration errors and signal con-
tentions—two situations that produce erroneous
processing, reduce system life, or even cause per-
manent system damage. Excessive chip heat can
also be caused by the peculiarities of a machine
configuration: Fine-grain pipelined data paths,
heavily loaded buses, or high off-chip capacitance
can lead to an unforeseen power overhead.
Consequently, the designers of configurable com-
puting machines can detect several failures by
adding some thermal monitoring mechanisms.
For years, temperature has been a primary
parameter of hardware debugging techniques.
In the past, low temperature identified bad vac-
uum tubes. Today, burning ICs points to poten-
tial problems. Even in the era of complex
instrumentation, hardware designers keep the
habit of detecting faulty circuits by touching the
chip packages. In this way, the increasing ten-
dency to include temperature sensors on cur-
rent electronic systems has been a natural step.
The concept of thermal testing, introduced in
Székely et al.,1is now incorporated into several
electronic products. For instance, thermal pro-
tections have been adopted in commercial con-
figurable computing machine boards,2,3and two
pins connected to an internal diode have been
recently included in a new FPGA series to sense
junction temperature.4Finally, semiconductor
manufacturers are offering complete families of
chips to control temperature on PC boards.5
An important difference between PC boards
and reconfigurable systems is that in the latter,
the processing tasks are dynamically distributed
between several chips that change their func-
tionality at the hardware level. As a consequence,
the detection of hot spots requires sensing the
temperature in each IC in the system. However,
if the machine is large, using classic thermal trans-
ducers is impractical. Thermocouples, thermis-
tors, or integrated sensors require both extra
wiring and hardware that must be immune to the
influence of the high-frequency signals usually
existing in the machine. Moreover, the designer
must pay attention to details like sensor posi-
tioning, thermal coupling, or analog instrumen-
tation. The implementation of on-chip sensors is
an alternative to avoid several of these inconve-
niences, but the main techniques6require a full-
custom chip redesign. Thus, the question is how
a system designer can insert thermal sensors
inside commercial reconfigurable chips. This arti-
cle explores three straightforward ways to solve
this problem: to construct ring-oscillators, to use
built-in oscillators available on many FPGAs, and,
finally, to reuse the I/O pad clamping diodes for
Some on-chip, end-user-oriented
alternatives to thermal testing
It is well-known that microelectronic delays
increase with temperature. As a consequence,
a way to measure chip heating is to construct
an oscillator and calibrate its output drift in
Thermal Testing on
Ring-oscillators are useful to monitor the thermal
status of reconfigurable computers. No analog
parts exist, and the sensors can be dynamically
inserted, moved, or eliminated.
Sergio Lopez-Buedo, Javier Garrido, and
Universidad Autónoma de Madrid
0740-7475/00/$10.00 © 2000 IEEE
MHz per °C or °F, an idea originally proposed
in Quenot et al.7This solution establishes a nat-
ural link between temperature (an analog mag-
nitude) and FPGAs (digital chips) through the
only analog magnitude that can be directly
measured by a digital circuit: the frequency.
A direct way to get frequencies in FPGAs is
to map a ring-oscillator. A ring-oscillator consists
of a feedback loop that includes an odd num-
ber of inverters needed to produce the phase
shifting that maintains the oscillation (Figure 1).
The resulting period is twice the sum of the
delays of all elements that compose the loop.
The inversions can be done using the look-up
tables (LUTs) of the configurable logic blocks
(CLBs) or the programmable inverters included
in the I/O blocks (IOBs) of the FPGA. In any
case, it is useful to insert an external signal to
open the loop, as well as an output buffer to pre-
vent frequency variations due to different loads.
The advantages of oscillators as thermal
transducers are multiple:
I They can be easily implemented with few
I Some FPGA families include built-in
I Like other on-chip sensors, the junction tem-
perature instead of the package temperature
I All signals are digital; thus, they can be
processed using the general resources of the
I The sensors are small: Practical circuits use
two logic blocks, and a minimum-size sen-
sor can be fitted in just an I/O block.
I A sensor or even an array of them can be
placed in any position of the chip, making
possible the construction of a thermal map
of the die.
I The sensors can be dynamically inserted,
moved, or eliminated.
During a discussion on an Internet news-
group, Peter Alfke suggested another ingenious
alternative to determine chip temperature:
measure the junction forward voltage of the
clamping diodes located in the FPGA pads.8
This technique lets the designer obtain free,
small, and abundant on-chip thermal sensors
at the cost of some external analog circuitry
and only one I/O pin. The method, also men-
tioned in Dewey and Emerald,9is based on the
voltage–current relationship in an ideal diode:
Isincludes six parameters that depend on the
temperature and nearly determine the overall
thermal characteristics of the junction. In short,
for a fixed diode voltage, the current rises
almost exponentially with T; meanwhile, for a
fixed current, the voltage across the junction
diminishes almost linearly with T.10Practical
applications11,12have used the second operation
mode. The main advantage of the diodes as
thermal transducers is their low sensitivity to
power supply variations. Figure 2 shows a sim-
Figure 1. A ring-oscillator scheme.
Figure 2. Bottom IOB clamping diode as thermal
plified structure of an I/O pad and the mea-
surement scheme utilized in this work: A current
sink circuit fixes 5 mA in the lower diode (the
pad output buffer must be tristated). A refine-
ment of this experiment should embrace differ-
ent diode currents in order to select the biasing
that produces the most linear response.13
Some test circuits
Ring-oscillators can be manually construct-
ed or use a standard automatic partitioning,
placement, and routing design flow. In the last
case, the designers must include high-level
directives to avoid the simplification of an even
number of inverters during the compilation
process. It is also useful to fit the inverters in dis-
tant LUTs to increase wiring delays. Note that
unusually in digital design, the goal here is to
decrease the operation frequency in order to
minimize the problems related to self-heating,
power consumption, and counter size.
In this article, we selected an array of four
identical ring-oscillators to illustrate some
aspects of thermal testing. Figure 3 depicts a
detailed layout of one of them. The oscillators
were manually placed and routed using four
CLBs to increase their oscillation period. They
have an overall loop delay of 35 ns: 23.2 ns cor-
responding to LUTs and 11.8 ns to wiring. The
outputs were buffered (via another CLB) to pre-
vent possible mismatching caused by different
output paths. Figure 4 shows the final layout of
the array (the picture includes the circuitry sit-
uated near the bottom left corner utilized to
produce short circuits in pads and internal
To perform an accurate sensor calibration,
the FPGA samples must be introduced in a tem-
perature-controlled oven (Figure 5). In our
case, to save time, a configuration with all the
transducers was downloaded, but just one was
enabled during its characterization. We mea-
sured chip temperature by placing an iron–con-
stantan (Fe–CuNi) thermocouple in the center
of the package. A set of long cables (close to
one meter) were necessary to externally con-
figure and control the FPGA, as well as to carry
the oscillator outputs outside the oven. To pre-
vent excessive power consumption in the sen-
sors due to these high off-chip loads, we
inserted a driver (type 74HC125) near the FPGA
to isolate the ring outputs from the cables.
A source of error in active thermal trans-
ducers is the own sensor dissipation. However,
performing the measurements during a short
enable window minimizes this problem. In our
Figure 3. Layout of ring5.
Figure 4. Array of identical sensors situated in the die corners,
named counterclockwise ring5 (top left) to ring8. The relationship
between chip area and sensor size can be observed.
case, the oscillator was first left running during
0.2 ms to stabilize the output. Then, we mea-
sured the frequency during 4 ms (Figure 6) and
stopped the oscillator. The procedure was
repeated every 250 ms. Both parameters were
obtained empirically, and they should be
reviewed in future FPGAs, considering that self-
heating effects will be more significant in the
next generation of ICs.14
Figure 7 shows the efficacy of this strategy.
The graph superposes the output frequency of
ring5 for two different operation modes: win-
dowed enabling and free-running operation.
Even though the temperature was held con-
stant to 22°C during the experiments, a fre-
quency drift of more than 129 KHz (equivalent
to 2.5°C) appeared in the free-running opera-
tion. This effect is negligible in the win-
Main characteristics of thermal
sensors on FPGAs
Figure 8 (next page) summarizes the main
characteristics of the transducers. See our pre-
vious experiments on circuits with several
LUT/wiring delay ratios as well as different
The ring-oscillators exhibit the most linear
response in the normal range of temperature
operation. Their outputs are situated in an inter-
mediate band of frequencies: between 21 MHz
and 27 MHz (Figure 8a). So, their values can be
easily managed by a low-cost microcontroller
if a prescaler is used. All array sensors have the
same temperature variation (−0.20% per °C),
but each one runs at a different frequency for a
given temperature. The maximum gap between
them is about 0.8 MHz, although the outputs of
rings 5 and 6 are almost identical.
Figure 8c summarizes an example of the
second alternative: the use of the internal oscil-
lator included in the XC4000 series FPGA.17In
this case, to facilitate the comparison with the
CLB-based rings, the 8-MHz output response of
the OSC4 cell was calibrated in terms of
Finally, Figure 8e presents the result of the last
option, the IOB diodes. From 20°C to 90°C, the
voltage drop ranges between 0.63 mV and 0.55
mV. The average output sensitivity is −0.21% per
°C. Similar results were obtained for 1-mA biasing.
Diodes were less linear than ring-oscillators, but
they have an interesting advantage as thermal sen-
sors: Their response is almost independent of
power supply variations. In effect, an important
Figure 5. Sensor calibration setup.
Setting time guard
Oscillator enable time
Figure 6. Windowed–enabled mode.
0 20 40 60 80100120
∆f = 129 KHz
error = 2.5 °C
Enabled during 4.2 ms
every 250 ms
Output frequency (MHz)
Figure 7. Self-heating error in ring5 calibration. Short enable
window versus continuous operation.
parameter of the transducers is the error caused
by power supply variations (see Figure 8b, Figure
8d, and Figure 8f). Ring-oscillators exhibit a linear
response in the operation range, but their fre-
quency drift (in percentage of output variation per
volt) is important: near 15% per volt (Figure 8b).
20 3040506070 8090 100
Output frequency (MHz)
3.2 KHz per mV
3.2 KHz per mV
Output frequency (MHz)
Power supply voltage (V)
20 3040 50
60 7080 90100
Output frequency (MHz)
Output frequency (MHz)
0 3 KHz per mV
Power supply volt (V)
20 30 4050 60 708090 100
Diode voltage drop (mV)
Power supply volt (V)
Diode voltage drop (mV)
−3 mV per voltage
Figure 8. (a), (c), and (e) Thermal response of ring-oscillators, OSC4 cell, and IOB diodes and (b), (d), and (f) their
corresponding power supply sensitivity.
The OSC4 cell and the IOB diodes have a lower
power supply sensitivity: 3.6% per °C and less than
1%, respectively (see Figure 8d and Figure 8f).
Two examples of thermal testing
To illustrate the sensitivity of the on-chip sen-
sors, we fixed pins 35 and 36 of a XC4005 FPGA
to opposite logic levels. Both pins are situated in
the bottom left corner, close to ring6. Then, we
produced an intentional short circuit between
these pins and monitored the array response.
The results are summarized in Figure 9a. It shows
the normalized frequency of the sensors (with
respect to their values at room temperature). In
t = 0, the short circuit begins, finishing at t = 25
sec. An analysis of the data indicates that all fre-
quencies decrease following a second-order
exponential; however, the decay is different for
each sensor. A peak temperature is detected by
ring6: almost 3°C higher than that measured in
the opposite corner. The temperatures in the
equidistant corners (ring5 and ring7) were
almost equivalent. The above experiment was
repeated for a short circuit produced in two
internal tristate buffers situated near ring6. Even
considering the small magnitudes involved in
this case, the behavior is similar to that obtained
in the previous test (Figure 9b).
Taking into account that chip failures
depend on not only the steady-state junction
temperature but also the temperature gradi-
ents,18this experiment also illustrated that the
ring-oscillators can be utilized to determine if a
significant difference of temperature exists in
the die during the operation.
THIS ARTICLE SUGGESTS some ideas to imple-
ment an online thermal monitoring strategy on
reconfigurable systems. The three alternatives
show different advantages. The best results in fre-
quency range, resource occupation, and power
supply sensitivity correspond to the built-in
XC4000 series oscillator. Meanwhile, CLB-based
ring-oscillators can be situated in virtually any
position of the chip. Pad diodes are also interest-
ing due to their lower power supply sensitivity.
The sensor calibration procedure can be
dropped if the goal is just to detect peak power
values. In this case, the adjustment can be done
in terms of power consumption by measuring
both chip input current and sensor output fre-
quency for each computer configuration and for
normal operation. Thus, the correct thermal sta-
tus of the machine can be described by a range
of expected frequency values in each FPGA.
These methods also facilitate the construc-
tion of highly reliable systems based on FPGAs.
Even considering that the advantages of the
thermal deration technique (the lowering of the
operating temperature to get an extra margin of
safety) is being reviewed,18,19the proposed trans-
ducers allow the designers to know the junction
temperature Tj for the actual operation condi-
tions. Thus, aspects like the thermal effects of
the printed circuit board,20the chip positioning,
the heat produced by neighboring devices, the
interferences in the air flow, the humidity, or the
details related to the heat sink utilized can be
Normalized output frequency
0510 15 20 25 30 35 40 45 50 55
T = 23°C
T = 24°C
T = 24.4°C
05 10 15 20 25 30 35 40 45 50 55
T = 30°C
T = 33°C
T = 23°C
Normalized output frequency
Figure 9. Normalized response of each sensor (with respect to
their frequencies at room temperature) for (a) pad and (b) internal-
incorporated into the deration strategy.
Finally, this work opens a new field of appli-
cation for FPGAs. The reconfiguration capabil-
ity transforms these devices into a powerful tool
for the study of thermal aspects of ICs and pack-
aging, allowing researchers to perform an
unlimited number of new experiments. Just the
possibility of “moving” the sensors along the die
is unthinkable in other VLSI technologies.
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Sergio López-Buedo is
currently working toward the
PhD at the Universidad
Autónoma de Madrid, where
he is an assistant professor of
computer architecture. His current research inter-
ests include the design of high-speed FPGA
design, low-power techniques,
arithmetics, reconfigurable systems, and Internet-
based EDA tools. He received the telecommuni-
cation engineering degree from the Universidad
Politécnica de Madrid (Spain) in 1997. He is a
member of IEEE.
Javier Garrido is currently
a titular professor of comput-
er architecture at the School
of Computer Engineering of
the Universidad Autónoma
de Madrid, Spain. His current research interests
are in the areas of semiconductor technologies
(such as dielectrics layers and III-V etching). He
is also involved in the design of FPGA-based sys-
tems and low-power techniques. He received the
BSc degree in 1974, the MSc degree in 1976,
and the PhD degree in 1984 in physics from the
Universidad Autónoma de Madrid (Spain). He is
a member of IEEE.
Eduardo I. Boemo is a tit-
ular professor of ASIC design
at the School of Computer
Engineering of the Universi-
dad Autónoma de Madrid,
Spain. His current research interests include the
design of FPGA-based systems, low-power
techniques, computer arithmetics, self-timed cir-
cuits, and electrical engineering education. He
received the electrical engineering degree from
the Universidad Nacional de Mar del Plata
(Argentine) and the PhD degree in telecommu-
nication engineering from the Universidad
Politécnica de Madrid (Spain) in 1985 and 1996,
Send comments and questions about this arti-
cle to Eduardo Boemo, School of Computer
Autónoma de Madrid, Ctra. de Colmenar Km.
15, 28049 Madrid, Spain.