The hybrid field-programmable architecture

Toronto Univ., Ont.
IEEE Design and Test of Computers (Impact Factor: 1.62). 05/1999; 16(2):74 - 83. DOI: 10.1109/54.765206
Source: DBLP


The authors propose a new architecture that combines two existing
technologies: lookup-table-based FPGAs and complex programmable logic
devices based on PLA-like blocks. Their mapping results indicate that on
average LUT-based FPGAs require 78% more area than their hybrid FPGA,
while providing roughly the same circuit depth

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    • "For example, the PLB in Fig. 3 cannot implement a three-input OR gate. Previous work solved this problem by using two main approaches. 1) A specialized PLB is proposed, and a customized mapping algorithm is implemented to map benchmark circuits to the proposed PLB [9]. 2) Functions are decomposed using specialized Boolean matching techniques such that it matched the structure of the PLB [10]. "
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    ABSTRACT: This paper presents a field-programmable gate array (FPGA) logic synthesis technique based upon Boolean satisfiability. This paper shows how to map any Boolean function into an arbitrary programmable logic block (PLB) architecture without any custom decomposition techniques. The authors illustrate several useful applications of this technique by showing how this technique can be used for architecture evaluation and area optimization. When evaluating the FPGA architecture, the authors focus on the basic building block of the FPGA, which they refer to as PLB. In order to illustrate the flexibility of their evaluation framework, several unrelated PLB architectures are evaluated in an automated fashion. Furthermore, the authors show that using their technique is able to reduce FPGA resource usage by 27% on average in common subcircuits found in digital design.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 08/2007; 26(7-26):1196 - 1210. DOI:10.1109/TCAD.2007.891362 · 1.00 Impact Factor
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    • "Previously, robust heuristics to answer this question fell into two categories: a specialized PLB is proposed and a customized mapping algorithm is implemented to map benchmark circuits using the proposed element [9]; specialized Boolean-matching techniques are developed to decompose a logic function in such a way so that it matches the structure of the proposed PLB [10]. Both of these techniques require a specific logic manipulation technique for each PLB which suffers a lack of generality. "
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    ABSTRACT: A novel field programmable gate array (FPGA) logic synthesis technique that determines if a logic function can be implemented in a given programmable circuit is presented, and how this problem can be formalised and solved using quantified Boolean satisfiability is described. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has many applications to FPGAs. The application demonstrated is the FPGA programmable logic block evaluation and the results show that this tool allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.
    IEE Proceedings - Computers and Digital Techniques 06/2006; DOI:10.1049/ip-cdt:20050164
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    • "The total area results are calculated in terms of 4-LUTs. We have made two assumptions based on our layout results presented in [6] [7]: 1) the area of a PALB and its routing equals the area of four 4-LUTs and their routing, and 2) the logic delay of a PALB is equal to the logic delay of a LUT. The results in the table show that the LUT-based FPGAs occupy 29% more silicon area than HFPA on average. "
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    ABSTRACT: In this paper we present new technology mapping algorithms for use in a programmable logic device (PLD) that contains both lookup tables (LUTs) and PLA-like blocks. The technology mapping algorithms partially collapse circuits to reduce either area or depth, and pack the circuits into a minimum number of LUTs and PLA-like blocks. Since no other technology mapping algorithm for this problem has been previously published, we cannot compare our approach to others. Instead, to illustrate the importance of this problem we use our algorithms to investigate the benefits provided by a PLD architecture with both LUTs and PLA-like blocks compared to a traditional LUT-based FPGA. The experimental results indicate that our mixed PLD architecture is more area-efficient than LUT-based FPGAs by up to 29%, or more depth-efficient by up to 75%.1
    Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays; 01/2000
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