The hybrid field-programmable architecture

Toronto Univ., Ont.
IEEE Design and Test of Computers (Impact Factor: 1.62). 05/1999; DOI: 10.1109/54.765206
Source: DBLP

ABSTRACT The authors propose a new architecture that combines two existing
technologies: lookup-table-based FPGAs and complex programmable logic
devices based on PLA-like blocks. Their mapping results indicate that on
average LUT-based FPGAs require 78% more area than their hybrid FPGA,
while providing roughly the same circuit depth

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    ABSTRACT: This paper presents a technology mapping algorithm that can be used to evaluate the robustness of any FPGA pro-grammable logic block (PLB). This algorithm, named SATMAP, uses Boolean satisfiability (SAT) to determine if a logic cone can be implemented in a given PLB. This al-gorithm is a fundamental tool needed to study the utility of any proposed FPGA logic block. Our approach is the first tool of its kind that allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.


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