The hybrid field-programmable architecture

Toronto Univ., Ont.
IEEE Design and Test of Computers (Impact Factor: 1.62). 05/1999; DOI: 10.1109/54.765206
Source: IEEE Xplore

ABSTRACT The authors propose a new architecture that combines two existing
technologies: lookup-table-based FPGAs and complex programmable logic
devices based on PLA-like blocks. Their mapping results indicate that on
average LUT-based FPGAs require 78% more area than their hybrid FPGA,
while providing roughly the same circuit depth

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    ABSTRACT: This paper presents a technology mapping algorithm that can be used to evaluate the robustness of any FPGA pro-grammable logic block (PLB). This algorithm, named SATMAP, uses Boolean satisfiability (SAT) to determine if a logic cone can be implemented in a given PLB. This al-gorithm is a fundamental tool needed to study the utility of any proposed FPGA logic block. Our approach is the first tool of its kind that allows radical new features of FPGA logic blocks to be evaluated in a rigorous scientific way.
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    ABSTRACT: In this article, we study the technology mapping problem for a novel field-programmable gate array (FPGA) architecture that is based on k-input single-output programmable logic array-(PLA-) like cells, or, k/m-macrocells. Each cell in this architecture can implement a single output function of up to k inputs and up to m product terms. We develop a very efficient technology mapping algorithm, k m flow, for this new type of architecture. The experimental results show that our algorithm can achieve depth-optimality on almost all the testcases in a set of 16 Microelectronics Center of North Carolina (MCNC) benchmarks. Furthermore it is shown that on this set of benchmarks, with only a relatively small number of product terms (m ≤ k + 3), the k/m-macrocell-based FPGAs can achieve the same or similar mapping depth compared with the traditional k-input single-output lookup table-(k-LUT-) based FPGAs. We also investigate the total area and delay of k/m-macrocell-based FPGAs and compare them with those of the commonly used 4-LUT-based FPGAs. The experimental results show that k/m-macrocell-based FPGAs can outperform 4-LUT-based FPGAs in terms of both delay and area after placement and routing by VPR on this set of benchmarks.
    ACM Transactions on Design Automation of Electronic Systems 01/2005; 10(1). DOI:10.1145/1044111.1044113 · 0.52 Impact Factor
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