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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007 719

An Exact Jumper-Insertion Algorithm for Antenna

Violation Avoidance/Fixing Considering

Routing Obstacles

Bor-Yiing Su, Yao-Wen Chang, Member, IEEE, and Jiang Hu, Member, IEEE

Abstract—We study in this paper the problem of jumper in-

sertion on general routing (Steiner/spanning) trees with obstacles

for antenna avoidance/fixing at the routing and/or postlayout

stages. We formulate the jumper insertion for antenna avoidance/

fixing as a tree-cutting problem and present the first optimal

algorithm for the general tree-cutting problem. We show that

the tree-cutting problem exhibits the properties of optimal sub-

structures and greedy choices. With these properties, we present

an O((V + D)lg D)-time optimal jumper-insertion algorithm

that uses the least number of jumpers to avoid/fix the antenna

violations on a Steiner/spanning tree with V vertices and D

obstacles. Experimental results show the superior effectiveness

and efficiency of our algorithm.

Index Terms—Antenna effect, design for manufacturability,

physical design, reliability, routing.

I. INTRODUCTION

A

jor concerns in the design and manufacturing of very large scale

integrated circuits. The fine feature size of modern IC tech-

nologies is typically achieved by using plasma-based processes.

In nanometer technology, more stringent process requirements

cause some advanced high-density plasma reactors adopted in

the production lines to achieve fine-line patterns [4]. However,

these plasma-based processes will charge conducting compo-

nents of a fabricated structure. As a result, the accumulated

charges may affect the quality of ICs. This is called the antenna

effect.

During metallization, long floating interconnects act as tem-

porary capacitors and accumulate charges gained from the

energy provided by fabrication steps such as plasma etching.

A random discharge of the floating node due to subsequent

process steps could permanently damage transistors in the IC

S PROCESS technology enters the nanometer era, prod-

uct reliability and manufacturing yield have become ma-

Manuscript received May 2, 2006; revised July 19, 2006. The work of

B.-Y. Su and Y.-W. Chang was supported by the National Science Council of

Taiwan, R.O.C., under Grant NSC 93-2815-C-002-046-E, Grant NSC 94-2215-

E-002-005, and Grant NSC 94-2752-E-002-008-PAE. The work of J. Hu was

supported by Semiconductor Research Corporation under Contract 2003-TJ-

1124. This paper was recommended by Guest Editor P. H. Madden.

B.-Y. Su is with the Department of Electrical Engineering, National Taiwan

University, Taipei 106, Taiwan, R.O.C. (e-mail: b90901130@ntu.edu.tw).

Y.-W. Chang is with the Graduate Institute of Electronics Engineering and

also with the Department of Electrical Engineering, National Taiwan Univer-

sity, Taipei 106, Taiwan, R.O.C. (e-mail: ywchang@cc.ee.ntu.edu.tw).

J. Hu is with the Department of Electrical Engineering, Texas A&M Univer-

sity, College Station, TX 77843 USA (e-mail: jianghu@ece.tamu.edu).

Digital Object Identifier 10.1109/TCAD.2007.892338

[6], [8]. For instance, the exposed polysilicon and metal struc-

tures connected to a thin-oxide transistor will collect charge

from the processing environment (e.g., reactive-ion etching)

and damage the transistor when the discharging current flows

through the thin oxide. The mechanism of antenna damage

is not fully understood, but there is experimental evidence

indicating when charging occurs and how it may affect the

quality of gate oxide [6], [8]. Charging occurs when conductor

layers, not covered by a shielding layer of oxide, are directly

exposedtoplasma.Theamountofsuchchargingisproportional

to this plasma-exposed area. If conductor layers are connected

to a diffusion-layer pattern, such charges are discharged to the

substrate through the diffusion (see Fig. 1 for an illustration).

On the other hand, if the charged conductor layers are con-

nected only to the gate oxide, Fowler–Nordheim tunneling

current through thin oxide discharges such charges and causes

damage to the thin oxide [9]; see Fig. 1(b) and (c). As shown

in Fig. 1, interconnects are manufactured layer by layer. Before

a conducting path to the diffusion is formed in metal-2-layer

pattern etching [see Fig. 1(d)], the interconnects in the poly and

metal 1 layers might have accumulated so many charges that

they cause damage on the gate in the left of Fig. 1(c) (note that

there will not be any antenna violation after a conducting path

to the diffusion is formed).

The following are popular solutions to reduce the antenna

effect [1].

1) Jumper insertion: Break the signal wires with antenna

violations and route them to the highest layers by jumper

insertion. This reduces the charge amount for violated

wires during manufacturing.

2) Diode insertion: Fix those wires with antenna violations

that have enough rooms for under-the-wire diode (or

reverse diode) insertion. During wafer manufacturing, all

the inserted diodes are floating (or ground). A diode or a

reverse diode can be used to protect all input ports that

are connected to the same output ports.

3) Embedded protection diode: Add protection diodes on

every input port of a standard cell.

4) Antenna-aware routing: Since the antenna effect mainly

occurs in the gate input (with high impedance) and sel-

dom occurs in the diffusion output (with low impedance

and drains out the plasma immediately) for current tech-

nology, an antenna-aware router can try to route the wire

with a high antenna-strength ratio at the diffusion output

and minimize the antenna-strength ratio at the gate input.

0278-0070/$25.00 © 2007 IEEE

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720 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007

Fig. 1.

pattern etching of (a). Charge on the left polypattern is discharged through the

gate while charge on the right polypattern is discharged through the diffusion.

(c) Late stage of metal-1-layer pattern etching of (a). Charge on the left

metal 1 pattern is discharged through the gate while charge on the right

metal 1 pattern is discharged through the diffusion. (d) Late stage of metal-2-

layer pattern etching. Charges on all the metal 2 patterns are discharged through

the diffusion.

Antenna effect. (a) Example routing. (b) Late stage of polylayer

Comparing the four methods, for method 3) of embedded

protection diode, since these diodes are embedded and fixed,

they consume unnecessary areas when there is no violation

at the connecting wire. For the second and third methods,

we need extra space in the chip to place the diodes. Because

the number of diodes needed for fixing antenna violations

grows dramatically as the feature shrinks, it is hard to preserve

enough space for diodes in nanometer IC designs. In order

to resolve this problem, the dynamic diode insertion during

the placement with bounding-box-timing estimation is used to

resolve this problem [10]. This functionality is embedded in

many commercial placers. For the fourth method, an already

complex router needs to additionally consider the antenna

effect, and the technique is less effective for fixing the antenna

violations. As a result, jumper insertion becomes one of the

mostpopularapproachesforavoiding/fixingantennaviolations.

The function of jumper insertion can be explained using Fig. 2.

In Fig. 2(a), when the metal 1 layer is manufactured, the gate

on the right might be damaged because the large area of the

metal 1 interconnection can accumulate sufficient charges to

damage the gate. However, if we insert a jumper to route

the interconnect on the metal 2 layer, as shown in Fig. 2(b),

Fig. 2.

inserting a jumper from metal 1 layer to metal 2 layer.

Jumper insertion. (a) Stage before inserting a jumper. (b) Stage after

Fig. 3.

needed for fixing the antenna violation if jumpers can be inserted only beside

tree nodes, as the assumption made in [3]. (b) One jumper suffices to fix the

antenna violation if jumpers can be inserted at an arbitrary position of the wire

segment, as the assumption made in [7].

Jumper insertion for a wire of 1.3 Lmax long. (a) Two jumpers are

the effective conductor layer becomes smaller. Therefore, the

stored charge is not enough to damage the gate on the right, and

thus, we can avoid the antenna violation.

Although jumper insertion is currently a very popular ap-

proach for antenna avoidance/fixing, jumpers induce vias that

will consume silicon areas and reduce circuit performance.

Therefore, it is desired to fix antenna violations by using the

minimum number of jumpers. The problem of jumper insertion

on a routing tree for antenna avoidance has attracted much

attention in the literature recently. Ho et al. in [3] propose an

O(V lgV )-time bottom-up approach to insert jumpers in a

spanning tree of V vertices for antenna avoidance. The work

assumes that each tree node corresponds to a gate terminal

and inserts jumpers only beside the tree nodes; its optimality

holds only for this special condition of inserting jumpers right

beside the nodes of a spanning tree. There are two recent works

that consider more general cases for jumper insertion on a

general routing tree (could be a spanning or Steiner tree). The

recent work [7] relaxes the constraint of inserting jumpers only

beside the tree nodes, for which jumpers can be inserted at an

arbitrary position of a tree edge. The work achieves the same

time complexity as [3] for the relaxed problem. As an example

shown in Fig. 3, the wire segment is of 1.3 Lmaxlong, where

Lmaxdenotes the upper bound for antenna (i.e., any wire longer

than Lmaxwill violate the antenna rule). For this wire segment,

the work in [3] needs two jumpers to fix the antenna violation

[see Fig. 3(a)] while a single jumper suffices for the work [7] to

fix the violation [see Fig. 3(b)].

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SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING721

Fig. 4.

jumpers c1,...,c4to solve the antenna violations. (c) This paper needs only

three jumpers c5, c6, and c7to satisfy the antenna rule.

(a) Routing tree with two sink nodes u1and u2. (b) Work in [9] needs

Another recent work [9] by Wu et al. extends the work in [3]

to handle either a spanning or a Steiner tree. With the imple-

mentation scheme proposed by Kundu and Misra [5], the work

in[9]canachievelinear-timecomplexityforjumperinsertionin

a Steiner/spanning tree for antenna avoidance/fixing. To fix the

antenna violation of a sink node (a gate terminal in this paper),

the work first removes all subtrees around the node that violate

the antenna rules. After all such subtrees are removed, if the

sink still violates the antenna rule, the work will continually

remove the heaviest branch from the sink until the antenna rules

aresatisfied.Thisapproachisoptimalonlyforsinknodesalone.

For the case with two adjacent sink nodes, their method might

not be optimal. As the routing-tree example shown in Fig. 4(a),

u1and u2are two sink nodes, the number beside each edge

denotes the antenna charge weight (measured by the ratio of

antenna strength (length, area, perimeter, etc.) to the gate size,

wirelength,wirearea,and/orwireperimeter)andthemaximum

antenna weight that a sink node can bear is assumed to be ten.

For the work in [9], since we cannot partition the tree into

any subtree with the total weight equal to ten, we will cut

the heaviest edge near the sink node until the antenna rule is

satisfied on u1and u2. Thus, the edge e(u1,u2) = 10 will be

removed first, and the work will insert four jumpers c1, c2, c3,

and c4, as shown in Fig. 4(b). Nevertheless, for this case, three

jumpers suffice to solve the antenna violations; see the jumpers

c1, c2, and c3shown in Fig. 4(c).

For a jumper-insertion algorithm to be practical, we shall

work on general routing (Steiner or spanning) trees, in which

a tree node represents a gate terminal and a Steiner node

represents a routing junction. We shall also allow a jumper

TABLE I

FEATURES OF THE RELATED JUMPER INSERTION WORKS

to be inserted at an arbitrary position of a tree edge. Since

jumper insertion routes a signal wire to the top most layer, we

must further consider the routing with obstacles in the active

layers—the layers from the current routing layer up to the

top most layer, which could be prerouted nets, power/ground

nets, clock nets, etc. A jumper-insertion algorithm that does

not work on Steiner trees, allow arbitrary jumper-insertion

position, or consider routing obstacles cannot be practical for

real applications.

In this paper, we consider the general case of inserting

jumpers at arbitrary positions of tree edges with obstacles for

antenna avoidance/fixing (see Table I for the features consid-

ered by the recent jumper-insertion algorithms). We formulate

the general jumper insertion for antenna avoidance (applicable

at the routing stage) and/or fixing (applicable at the postlayout

stage) with obstacles as a tree-cutting problem on a Stenier/

spanning tree and present the first optimal algorithm for the

general tree-cutting problem. We show that the tree-cutting

problem exhibits the properties of optimal substructures and

greedy choices. With these properties, a greedy algorithm

suffices to find an optimal solution [2]. Based on the theory,

we present an O((V + D)lgD)-time optimal jumper-insertion

algorithm that uses the minimum number of jumpers to fix the

antenna violations in a Steiner/spanning tree with V vertices

and D obstacles. Experimental results show that our algorithm

is very efficient and effective.

The remainder of this paper is organized as follows.

Section II formulates the problem of jumper insertion on a

Steiner/spanning tree with obstacles for antenna avoidance/

fixing. Section III presents an optimal algorithm for the

proposed problem. Section IV proves the optimality of the

algorithm. Section V analyzes the complexity of the algo-

rithm. Section VI extends the algorithm to the handling of

the antenna-strength-to-gate-size model. Section VII reports

the experimental results. Finally, the conclusions are given

in Section VIII.

II. PROBLEM DEFINITION

Before formulating our problem, we first list the notation

used in this paper in Table II for clarity.

To avoid/fix the antenna violation, we require that the to-

tal effective conductor connecting to a gate be less than or

equal to a threshold Lmax. The threshold could be the ratio

of antenna strength (length, area, perimeter, etc.) to the gate

size, wire-area limit, wire-perimeter limit, wire-length limit,

or any model of the strength of antenna effect caused by

conductors. For example, for wire area, we can simply compute

the product of the wire length and the wire width (size); for the

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722 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007

TABLE II

NOTATION USED IN THE ALGORITHM

Fig. 5.

accumulated on edges e(u,s), e(s,v1), and e(s,v2) will all cause antenna

effect on u.

u, v1, and v2are gate terminals, and s is a Steiner point. The charges

antenna-strength-to-gate-size ratio, we can simply model the

antenna strength divided by the gate size as the edge weight.

It will be clear later in Section VI that the modeling of the

antenna-strength-to-gate-size ratio is still feasible, since our ap-

proach processes gate by gate for the antenna avoidance/fixing.

Typically, a net is modeled as a routing tree, where a node in

the tree denotes a circuit terminal/junction (a gate, diffusion,

or junction of interconnects) and an edge denotes the inter-

connection between two circuit terminals or junctions. Since

the interconnection connecting to a diffusion terminal will not

cause any antenna violation, as explained in Section I, we shall

focus on those connecting to gate terminals.

Let T = (V = VG∪ VN,E) be a Steiner tree. The set VG

of the nodes represents all gate terminals, the set VN of the

nodes represents all Steiner points, the set E of the edges

denotes the wires connecting the circuit terminals or junctions,

and an edge weight gives the measure of the wires with the

same unit as Lmax. Note that a Steiner point denotes a wire

junction, which cannot help discharge the wire (see Fig. 5

for an illustration). The charges accumulated on edges e(u,s),

e(s,v1), and e(s,v2) will all cause antenna effect on the gate

terminal u (we shall focus on Steiner trees in the following

discussions; the proposed method readily applies to spanning

trees, for which VN= ∅).

For example, if Lmaxis a wire-length limit, an edge weight

denotesthewirelengthbetweentwocircuitterminals/junctions.

If Lmax is a wire-area limit, the edge weight denotes the

wire area (and so is the ratio of antenna strength to the gate

size). A gate will violate the antenna rule if the effective

conductor incident on the gate (i.e., the effective weight—the

sum of the weights of the edges incident on the corresponding

node) is larger than Lmax. To reduce the antenna effects on

Fig. 6.

are cutting nodes. Therefore, the sum of effective edge weights of u1, u2, and

u3are: L(u1) = l(u1,u2) + l(u1,c1) + l(u1,s1) + l(s1,u3) + l(s1,c2),

L(u2) = l(u1,u2), L(u3) = l(u1,s1) + l(s1,u3) + l(s1,c2).

u1, u2, and u3are gate terminals. s1is a Steiner point. c1and c2

a gate, we can apply the technique illustrated in Fig. 2 by

adding a jumper on a wire connecting to the gate to reduce

the effective conductor. This operation is modeled as adding

a cutting node on the tree edge corresponding to the wire to

reduce the effective edge weight associated with the gate node.

As aforementioned, jumpers are implemented by vias, which

will consume silicon areas and reduce circuit performance.

Therefore, it is desired to fix antenna violations by using the

minimum number of jumpers. In other words, given a routing

tree (V = VG∪ VN,E) and an upper bound on the antenna

Lmax, we intend to add the minimum number of cutting nodes

on the tree edges so that the effective edge weight associated

with each node is smaller than Lmax. Let p(u) denote the

node u’s parent. Let L(u) denote the sum of the effective edge

weights (strength ratio, wire lengths, wire areas, wire perimeter,

etc.) on node u (see Fig. 6 as an illustration). Let D be the set

of obstacles in the active layers (for simplicity, we focus our

discussions on the rectangular obstacles; the jumper-insertion

algorithm to be presented in this paper readily applies to the

problem with obstacles of arbitrary shapes, with additional

procedures for obstacle identification). The projection of the

obstacles in D defines the forbidden regions for the edges and

nodes of a routing tree for jumper insertion. Let F be the

set of the forbidden regions. Given a node u (an edge or a

tree segment e) of a routing tree, f(u) = 1 (f(e) = 1) if the

node u (the edge/segment e) falls inside the forbidden regions

(u ∈ F); f(u) = 0 (f(e) = 0), otherwise. With the definitions

above, we can formulate the addressed problem as follows.

Problem Jumper Insertion on a Routing tree with Obstacles

for Antenna (JIROA) avoidance/fixing: Given a routing tree

T = (V = VG∪ VN,E), an upper bound Lmax, and a set D of

rectangular obstacles, find the minimum set C of cutting nodes

on edges c ?= u for any c ∈ C and u ∈ V and f(c) = 0 for any

c ∈ C, so that L(u) ≤ Lmax, ∀u ∈ VG.

Note that the routing tree in this formulation represents a net

in any layout design stage, e.g., a net to be globally routed, a net

after detailed routing (in the postlayout stage). Therefore, the

JIROA problem is applicable to the antenna estimation in the

global/detailed routing stage and the antenna violation fixing in

the postlayout stage.

III. ALGORITHM FOR FINDING THE MINIMUM |C|

For the JIROA problem, we present in this section an

O((V + D)lgD)-time optimal algorithm, named Bottom Up

Jumper Insertion with Obstacles (BUJIO), for finding the mini-

mum cutting set C for a given routing (Steiner or spanning) tree

T = (V,E) with V nodes and D obstacles (note that we use V

to denote the set or the number of nodes in a routing tree, which

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Fig. 7.

Subroutines EqualLess and More to deal with the subleaf nodes.

Algorithm BUJIO deals with the leaf nodes first and, then, call

Fig. 8.

region.

Illustration of the r(u,v) function, where c is just beside the forbidden

is common in the community of computer science; its meaning

is clear from the context). Algorithm BUJIO is summarized

in Fig. 7.

Let l(e) (or l(u,v)) be the weight (could be the strength ratio,

wire length, wire area, wire perimeter, etc.) of the edge e =

(u,v) in T. In the BUJIO algorithm, we add the cutting nodes

into the original tree in a bottom-up manner. We first define a

subleaf node and an optimal replacement function r(u,v) (see

Fig. 8 for an illustration) as follows.

Definition 1: A subleaf is a node for which all its children

are leaf nodes, and if any of its children is a gate terminal, the

edges between it and its children all have weights ≤ Lmax.

Definition 2: Let u and v be two adjacent nodes with

f(v) = 1. Then, r(u,v) denotes the cutting node c on edge

e = (u,v) with f(c) = 0 and l(u,c) being the maximum

Fig. 9.

in an obstacle (denoted by the shaded region), where d1,d2,...,d5 are

nodes on the tree edges, just beside the obstacle. (b) Reducing the tree of

(a) by removing edges e(u,d1),e(u,d2),...,e(u,d5) and assigning w(u) =

?5

Example reduction for Step 2). (a) Routing tree with a node u

i=1l(e(u,di)).

among every node on edge e(u,v). In other words, c is just

beside the forbidden region covering node v (see Fig. 8).

We derive the BUJIO algorithm based on the following

four steps.

Step 1) Line 1 of Algorithm BUJIO: Sort the obstacles in D

by the x-axes and then the y-axes.

With this process, we can determine f(u) and f(e)

in O(lgD) time.

Step 2) Lines 2–4 of Algorithm BUJIO: We compute the

weight of every node.

If a tree node u ∈ V is in a forbidden region, some

segments of the edges incident on u could also

be in the forbidden region. Therefore, we cannot

insert jumpers on these segments, and charges in-

duced from these segments cannot be removed. We

use weight w(u) to record such information. That

is, w(u) =?

w(u) > Lmax for some node u, the accumulated

charges on u are over the upper bound that u can

tolerate. For this case, we cannot prevent node u

from antenna violation by jumper insertion alone.

Otherwise, we can always find an optimal solution

for jumper insertion. For the feasible case of a set

of edges incident on a node u, we can reduce the

problem with obstacles into the case without any ob-

staclebycontractingthetreesegmentse1,e2,...,ek

inside the obstacles to node u and assigning w(u) =

?k

processing, we can insert jumpers just as the case

without any obstacles.

Step 3) Lines6–15ofAlgorithmBUJIO:Wedealwithevery

leaf node.

In this step, our main goal is to prevent every leaf

node from antenna violation. Obviously, if we have

dealt with a leaf node, we need not consider it

any more. Therefore, line 7 of the BUJIO algo-

rithm marks these nodes to make sure that every

leaf node is processed only once. If l(u,p(u)) +

w(u) ≤ Lmax, the leaf node u satisfies the antenna

f(e)=1∧eincidentonul(e). Obviously, if

i=1l(ei) (see Fig. 9 for an illustration). After this

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Fig. 10.

c is the optimal one among the nodes on edge e(u,p(u)). (b) c1is the optimal

substitute of c, where c1= r(u,c) is just beside the forbidden region.

Explanation of lines 6–15 in the BUJIO algorithm. (a) Cutting node

rule. Thus, we need not insert any cutting nodes.

If u ∈ VN, since u is not a gate terminal, we

need not insert any cutting node either. However,

if l(u,p(u)) + w(u) > Lmaxand u ∈ VG, we must

insert at least one cutting node to satisfy that L(u) ≤

Lmax. We claim that l(u,c) = Lmax− w(u) (and

thus, l(c,p(u)) = l(u,p(u)) − Lmax+ w(u)) gives

the best position for inserting the cutting node; see

Fig. 10(a) for an illustration. However, if f(c) = 1,

we must find a position not in F. We claim that

c1= r(u,c) is the optimal substitute; see Fig. 10(b)

for an illustration. After adding jumper c or c1into

C, we cut edge e(u,c) or e(u,c1) from the tree T

(lines 6–15 in BUJIO).

Step 4) Lines 16–24 of Algorithm BUJIO: We deal with

every subleaf node.

In this step, our main goal is to prevent every subleaf

node from antenna violation. Moreover, we delete

some nodes and edges to make each subleaf node

a leaf node (note that as the edges are chopped

off in tree cutting, the leaf nodes of the remaining

tree might be Steiner or cutting nodes, which may

not always correspond to gate terminals). First of

all, if up and all its children are in VN, none of

them needs to satisfy the antenna rule. Therefore,

we just combine upand its children into a new leaf

node and modify its weight as w(up) + totallen

(see lines 18–20 in Algorithm BUJIO). Then, we

classify the subleaf nodes into two cases by the

sum of the edge weights between the node and its

children and the weights of its children. Let upbe a

subleaf node and ui,∀1 ≤ i ≤ k, be its children. Let

totallen =?k

as an illustration).

Case 4.1) totallen + w(up) ≤ Lmax.

We use the EqualLess subroutine to

deal with this case. If up and its

children form an isolated component,

they must satisfy the antenna rule, and

thus, we are done with the subroutine.

If totallen + w(up) + l(up,p(up)) ≤

Lmax, up will not violate the an-

tenna rule. If up∈ VN, it must be a

Steiner node and all the edges be-

tween up and its children contribute

to its weight. Thus, we simply com-

bine up and its children into a new

leaf node and modify its weight as

w(up) + totallen (see lines 4–5 in

i=1(l(ui,up) + w(ui)) (see Fig. 11

Fig. 11.

l(up,u2) + w(u2) + l(up,u3) + w(u3).

upis a subleaf node. Therefore, totallen = l(up,u1) + w(u1) +

Fig. 12.

w(u1) + l(up,u2) + w(u2) + w(up) + l(up,c) = Lmax. (b) Illustration

of the EqualLess subroutine with the cutting node c in a forbidden region.

Here, c1is the optimal substitute of c, where c1= r(up,c) is just beside the

forbidden region. (c) Illustration of the More subroutine.

(a) Illustration of the EqualLess subroutine. Here, l(up,u1) +

Subroutine EqualLess). Moreover, if

upor any of its children is in VG, it

means that the new leaf node upsatis-

fies the antenna rule, and thus, we add

upinto VG. Otherwise, we let upbe its

original type. If totallen + w(up) +

l(up,p(up)) > Lmax, we must add at

least one cutting node c to prevent

upfrom antenna violation. We claim

that l(c,up) + w(up) + totallen =

Lmaxgives the best position for insert-

ing the cutting node; see Fig. 12(a).

If f(c) = 1, however, we must find

a position not in F. We claim that

c1= r(up,c) is the optimal substitute;

see Fig. 12(b) for an illustration.

Therefore, we add c or c1into C and

cut up and all its children from the

original tree T (lines 10–17 in Fig. 13).

Case 4.2) totallen + w(up) > Lmax.

For this case, we apply the More sub-

routine summarized in Fig. 14. We first

introduce the set S = ∪k

up)) + w(ui)} from the subleaf node

upand its k children. Then, we apply

i=1{l(e(ui,

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SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING725

Fig. 13. Compute the case where totallen + w(up) ≤ Lmax.

the linear-time algorithm SPLIT pre-

sented in [5] to split the set S into

two disjoint subsets, Shand Sl, where

Shis the higher subset and Slis the

lower subset (to make this paper self-

contained, we also give the SPLIT

algorithm in Fig. 15). The two sub-

sets have three important properties:

1) for any a ∈ Sl and any b ∈ Sh,

we have a ≤ b; 2)?

w(up); and 3) for any b ∈ Sh, we have

?

over, the SPLIT algorithm will re-

turn the Sh subset. We claim that ci

on edge e(ui,up) with l(ci,up) = 0

(and, thus, l(ci,ui) = l(up,ui)) and

l(e(ui,up)) + w(ui) ∈ Sh, ∀1 ≤ i ≤

|Sh| gives the best positions for insert-

ing the cutting nodes; see Fig. 12(c).

Therefore, we add c1,...,c|Sh|into C

and cut ui,...,u|Sh|from the original

tree T (lines 1–5 in More). Moreover,

wecallsubroutineEqualLesstofurther

reduce upinto a new leaf node (line 6

in More).

s∈Sls ≤ Lmax−

s∈Sls + b > Lmax− w(up). More-

When |VG| = 0, Algorithm BUJIO terminates and C gives a

cutting set of the minimum size.

IV. PROOF OF THE OPTIMALITY OF |C|

Algorithm BUJIO is greedy in nature. To prove that

Algorithm BUJIO finds the optimal cutting set (of the minimum

size), therefore, we can show that the JIROA problem exhibits

optimal substructure and has the greedy-choice property [2].

Fig. 14.Compute the case where totallen + w(up) > Lmax.

Fig. 15.

finds the median m of set S and partitions S into two subsets Sland Sh,

where each element in Slis ≤ m and each element in Shis ≥ m. Moreover,

|Sh| ≤ |Sl| ≤ |Sh| + 1.

Return the required subset Shfrom S. Median-find-and-halve (S)

A problem exhibits optimal substructure if an optimal solution

to the problem contains within it optimal solutions to the

subproblems; a problem has the greedy-choice property if a

globally optimal solution can be arrived at by making a locally

optimal (greedy) choice [2].

Theorem 1: The JIROA problem exhibits an optimal

substructure.

Proof: We prove this property by contradiction. Given a

tree T = (V,E), suppose that the cutting set C is the optimal

solution of the tree. Every cutting node in C cuts the given

tree into two subtrees. Let some cutting node c ∈ C cut T

into subtrees T1 and T2. Let the cutting set C1⊆ C (C2⊆

C) be the set of cutting nodes in T1 (T2). Thus, C = C1∪

C2∪ {c}. If C1 does not form an optimal solution on T1,

let C?

Let C?= C?

|C1| + |C2| + 1 = |C|. This contradicts the assumption of the

optimality of set C. Therefore, the JIROA problem exhibits an

optimal substructure.

Now, we show that the JIROA problem has the greedy-

choice property, and Algorithm BUJIO finds the best solution

in each step. First, we show that Algorithm BUJIO has

the greedy-choice property among all leaf nodes. Then, we

show that BUJIO has greedy-choice property among all

subleaf nodes.

1be the optimal solution on T1, and thus, |C?

1∪ C2∪ {c}. We have |C?| = |C?

1| < |C1|.

1| + |C2| + 1 <

?

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726 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007

Lemma 1: Lines 6–15 of Algorithm BUJIO finds the best

cutting set of the minimum size so that every leaf node u ∈

VGsatisfies the antenna rule (i.e., L(u) ≤ Lmax, ∀ leaf nodes

u ∈ VG).

Proof: If l(u,p(u)) ≤ Lmax, the leaf node u must satisfy

the antenna rule, and thus, we do nothing. Otherwise, we

must insert at least one cutting node between u and p(u) to

prevent u from antenna violation. The possible cutting range

is represented by a thick line in Fig. 10(a). Let the optimal

solution add the cutting node c?between u and upwith L(u) ≤

Lmaxand L(p(u)) ≤ Lmax. We have l(c,p(u)) = l(u,p(u)) −

Lmax+ w(u) ≤ l(c?,p(u)). If we replace c?with c, the antenna

rule that L(u) ≤ Lmax is satisfied and the antenna rule that

L(p(u)) ≤ Lmaxis more tightly satisfied. Therefore, among all

nodes on the cutting range, c is the best position for adding a

cutting node.

Moreover, if f(c) = 1, we must find a substitute for the

cutting node c. The possible substitution range is represented

by a thick line in Fig. 10(b). Let the optimal solution se-

lect the cutting node c?

Lmax and L(p(u)) ≤ Lmax. Because l(c1,u) ≥ l(c?

l(c1,p(u)) ≤ l(c?

rule that L(u) ≤ Lmaxis still satisfied and the antenna rule that

L(p(u)) ≤ Lmax is more tightly satisfied. Therefore, among

all possible substitution nodes on edge e(u,c), c1is the best

substitute.

We proceed to show that lines 16–21 in BUJIO finds the best

cutting set of the minimum size for each subleaf node up. In

this step, we classify the subleaf nodes into two cases based on

the sum of the weights between upand its children uiand ui’s

weight records w(ui):

?k

Lmaxand?k

fore, we show that each case is with the greedy-choice property,

and we find the best cutting set for each case.

Lemma 2: Subroutine EqualLess finds the best cutting set of

the minimum size so that every subleaf node up∈ VGsatisfies

the antenna rule (i.e., L(up) ≤ Lmax, ∀ subleaf nodes up∈ VG

satisfying?k

up= p(ui)).

Proof: If upand its children form an isolated component,

they must satisfy the antenna rule, and thus, we do nothing. If

?k

satisfied, upsatisfies the antenna rule, and thus, we need no

cutting node. Otherwise, because?k

w(up) + l(up,p(up))>Lmax, we need to insert at least

one cutting node to maintain L(up) ≤ Lmax. Therefore, the

least number of cutting nodes is one. The possible cutting

range is represented by a thick line in Fig. 12(a). Suppose

that the optimal solution adds the cutting node c?other than

c to maintain L(up) ≤ Lmax and L(p(up)) ≤ Lmax. We

have

l(c,p(up)) = l(up,p(up)) − l(c,up) ≤ l(c?,p(up)) =

l(up,p(up)) − l(c?,up). If we replace c?with c, L(up) ≤ Lmax

issatisfied and

L(p(up)) ≤ Lmax

tightly. Therefore, c is the best position for adding the

cutting node.

Moreover, if f(c) = 1, we must find a substitute for cut-

ting node c. The possible substitution range is represented

1between u and c with L(u) ≤

1,u) and

1,p(u)), if we replace c?

1with c1, the antenna

?

i=1(l(up,ui) + w(ui)) + w(up) ≤

i=1(l(up,ui) + w(ui)) + w(up) > Lmax. There-

i=1(l(up,ui) + w(ui)) + w(up) ≤ Lmax, where

i=1(l(ui,up) + w(ui)) + w(up) + l(up,p(up)) ≤ Lmax is

i=1(l(ui,up) + w(ui)) +

issatisfiedmore

by a thick line in Fig. 12(b). Let the optimal solution se-

lect the cutting node c?

LmaxandL(p(up)) ≤ Lmax.Becausel(c1,up) ≥ l(c?

l(c1,p(up)) ≤ l(c?

tenna rule that L(up) ≤ Lmaxis still satisfied and the antenna

rule that L(p(up)) ≤ Lmax is more tightly satisfied. There-

fore, among all possible substitution nodes, c1 is the best

substitute.

Lemma 3: Subroutine More finds the best cutting set of the

minimum size so that every subleaf node up∈ VGsatisfies the

antenna rule (i.e., L(up) ≤ Lmax, ∀ subleaf nodes up∈ VG

satisfying?k

up= p(ui)).

Proof: By the proof of [5], we know that the set S = Sl∪

Shhas the following three properties.

1between up and c with L(up) ≤

1,up)and

1,p(up)), if we replace c?

1with c1, the an-

?

i=1(l(up,ui) + w(ui)) + w(up) > Lmax, where

Step 1) For any a ∈ Sland any b ∈ Sh, we have a ≤ b.

Step 2)

?

Step 3) For any b ∈ Sh, we have?

w(up).

s∈Sls ≤ Lmax− w(up).

s∈Sls + b > Lmax−

Using the properties above, we can easily verify that Sl

is the set with

?

the set is maximized. Moreover, if two or more sets have

the same maximum size and satisfy the same summation

rule, Sl is the one with the minimum?

?

the set, but we must add cutting nodes on every edge in

Sh. Since Sl’s size is maximized, the minimum number of

cutting nodes is |S| − |Sl| = |Sh|. Moreover, every edge

e(ui,up) with {l(e(ui,up)) + w(ui)} ∈ Sh needs a cutting

node. The cutting range of every edge e(ui,up) is represented

by the thick line shown in Fig. 12(c). Let the optimal solution

choose the set S?

|Sl| such that the optimal solution do not add any jumper

on the edge e(u?

Also, let the optimal solution select |Sh| cutting nodes c?

c?

s∈Sls ≤ Lmax− w(up), and the size of

s∈Sls value. Since

s∈Sls ≤ Lmax− w(up), we need no cutting nodes inside

l(and S?

h= S \ S?

l) with the optimal size

i,up) so that {l(e(u?

i,up)) + w(u?

i)} ∈ S?

h.

1,

2,...,c?

?

s∈Sls ≤?

l(up,p(up)) ≤ L?(up)=?

l(up,p(up)). Thus, if we replace each c?

on upis satisfied more tightly. Therefore, c1,...,c|Sh|are the

best positions for adding the cutting nodes. As a result, we can

cut the original tree T and call Subroutine EqualLess (line 6 in

More) to further reduce upinto a leaf node.

Based on the above theorem and lemmas, we have the

following theorem.

Theorem 2: The BUJIO algorithm finds an optimal solution.

Proof: By Lemmas 2 and 3, lines 16–21 of Algorithm

BUJIO exhibit the greedy-choice property on subleaf nodes.

Moreover, by Lemma 1, lines 6–15 of Algorithm BUJIO also

have the greedy-choice property on leaf nodes. Therefore,

Algorithm BUJIO has the greedy-choice property on both leaf

nodes and subleaf nodes. Since Algorithm BUJIO has the

greedy-choice property and the JIROA problem has optimal

substructure (by Theorem 1), Algorithm BUJIO finds an op-

timal cutting set.

|Sh|. Since l(ci,up)=0 ≤ l(c?

s?∈S?

i,up), ∀1 ≤ i ≤ |Sh| and

s∈Sls+ w(up)+?|Sh|

ls?+w(up)+?|Sh|

iby ci, the antenna rule

ls?, L(up)=?

i=10 +

i,up) +

s?∈S?

i=1l(c?

?

?

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SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING727

V. COMPLEXITY ANALYSIS

We analyze the time and space complexity of Algorithm

BUJIO in this section.

A. Time Complexity

In Step 1), it takes O(DlgD) time to sort the obstacles,

where D is the number of obstacles. The BUJIO algorithm

applies a bottom-up method to find the optimal solution on

the routing tree. In Step 2) of the BUJIO algorithm, it needs

O(V + E) time to compute the weights of all nodes. Since

O(E) = O(V ) in a tree, this step requires O(V ) time. In Steps

2) and 3) of the BUJIO algorithm, we consider each leaf and

each subleaf node only once. Since every node in the tree might

be a subleaf and might be cut into a leaf, we traverse each

node at most twice. When we traverse a leaf node, we need

at most O(lgD) times to check whether the cutting node c is in

the forbidden region or not. When we traverse subleaf nodes

using Subroutine EqualLess, at most we also need O(lgD)

time to check whether the cutting node c is in the forbidden

regionornot.InSubroutineMore,weusethelinear-timeSPLIT

algorithm to find the set Sh, and the algorithm requires constant

time on each node. Then, we need constant time to cut the

tree and call Subroutine EqualLess. Thus, the More subroutine

requires constant time on each node. To sum up, we traverse

each node at most twice, and in each traversal, we compute

each node at most O(lgD) times. Therefore, the total time

complexity of the BUJIO algorithm is O(DlgD) + O(V ) +

O(V lgD) = O((V + D)lgD).

B. Space Complexity

All we need to save are the tree T, the weight records w,

and the cutting set C. A tree needs only O(V + E) = O(V )

space. The weight records need O(V ) space. Moreover, accord-

ing to the algorithm, we add at most one cutting node for each

leaf node. Therefore, we need O(V ) space to keep the set C.

Thus, the total space complexity is O(V ).

Theorem 3: Algorithm BUJIO optimally solves the JIROA

problem in O((V + D)lgD) time using O(V ) space, where V

is the number of vertices in the given routing tree and D is the

number of obstacles.

VI. EXTENSIONS

For the JIROA problem, the BUJIO algorithm is mainly

based on the wire length, perimeter, and area measures for the

antenna-strength model. We discuss in this section for solving

the antenna problem under the antenna-strength-to-gate-size

ratio model.

A. Problem Definition

Let u be a gate terminal. Let A(u) denotes the area of the

gate terminal u. Let Rmaxbe the ratio upper bound. That is,

for a gate terminal u, if the total wire length (perimeter or

area) associated with u divided by A(u) is larger than Rmax,

then u will be damaged because of its antenna effect. With

these definitions, we reformulate the problem as follows. Prob-

lem JIROA under the antenna-strength-to-gate-size ratio model

(JIROA-R): Given a routing tree T = (V = VG∪ VN,E), an

upper bound Rmax, and a set D of rectangular obstacles, find

the minimum set C of cutting nodes, c ?= u for any c ∈ C and

u ∈ V , f(c) = 0 for any c ∈ C, so that L(u)/A(u) ≤ Rmax,

∀u ∈ VG.

B. Algorithm for Solving the JIROA-R Problem

The JIROA-R problem can be solved by the BUJIO algo-

rithm with minor modifications. For the JIROA-R problem,

we present here an O((V + D)lgD)-time optimal algorithm,

named Algorithm BUJIO under the antenna-strength-to-gate-

size ratio model (BUJIO-R), for finding the minimum cutting

set C for a given routing (Steiner or spanning) tree T = (V,E)

with V nodes and D obstacles. The only modification of

BUJIO-R from BUJIO can be explained as follows: In BUJIO-

R, we compute the accumulated edge weight as in BUJIO. To

make some gate terminal u satisfy the antenna rule, however,

we must let the antenna ratio associated with u smaller or equal

to Rmax (i.e., L(u)/A(u) ≤ Rmax). In order to describe the

BUJIO-R algorithm, we need to define a function here.

Definiton 3: Let up be a subleaf node and u1,u2,...,uk

denote the children nodes of up. If upis a Steiner point, and

some of up’s children are gate terminals, the function mA(up)

defines the minimum gate size among up’s children. That is,

mA(up) = min{A(ui) : uiis a gate terminal 1 ≤ i ≤ k}.

Algorithm BUJIO-R is summarized in Fig. 16 and explained

below.

Steps 1) and 2) Lines 1–4 of Algorithm BUJIO-R: The same

as BUJIO.

Step 3) Lines 6–15 of Algorithm BUJIO-R: Deal with

every leaf node. We use (l(u,p(u)) + w(u))/A(u)

(instead of l(u,p(u)) + w(u)) in line 8 to check

whether node u satisfies the antenna rule or not.

Moreover, if u violates the antenna rule, we have

to find a cutting node c such that u just reaches

the antenna upper bound Rmax. That is, we make

(l(u,c) + w(u))/A(u) = Rmax. Therefore, c is at

the position with l(u,c) = Rmax× A(u) − w(u).

The other processes in this part remain the same.

Step 4) Lines 16–27 of BUJIO-R: Deal with every sub-

leaf node.

We use (totallen + w(up))/A(up) (instead of

totallen + w(up)) in line 24 as the classification.

However, if upis a Steiner point and some of its

children are gate terminals, we must redefine the

A(up) value. We make the whole subtree rooted

at upas a group that needs to satisfy the antenna

rules. Moreover, according to the antenna-strength-

to-gate-size ratio model, the gate terminal with the

smallest gate size is the weakest one to suffer the

antenna violation. Therefore, if the gate terminal

of the smallest gate size among the whole subtree

satisfies the antenna rule, then all the gate terminals

connecting to up must satisfy the rule. Thus, we

make A(up) ← mA(up) (lines 22–23 of Algorithm

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728 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007

Fig. 16.

Subroutines EqualLess-R and More-R to deal with the subleaf nodes.

Algorithm BUJIO-R deals with the leaf nodes first and, then, call

BUJIO-R). Furthermore, if upsatisfies the antenna

rule, the smallest gate terminal in the subtree will

also satisfy the antenna rule and so will other gate

terminals in the subtree.

We discuss the processing in three cases as

follows.

Case 4.1) The same as the BUJIO algorithm.

Case 4.2) (totallen+w(up))/A(up)≤Rmax, for

this case, we apply the EqualLess-R

subroutine; see Fig. 17. We use

(totallen + w(up) + l(up,p(up)))/

A(up) (instead of totallen+ w(up) +

l(up,p(up))) in line 3 to check

whether node upsatisfies the antenna

rule or not. Moreover, if upviolates the

antenna rule, we must find a cutting

Fig. 17.Compute the case where (totallen + w(up))/A(up) ≤ Rmax.

Fig. 18.Compute the case where (totallen + w(up))/A(up) > Rmax.

node c such that up just reaches the

antenna upper bound Rmax. That is,

we have to make (totallen + w(up) +

l(c,up)))/A(up) = Rmax. Therefore,

c is at the position with l(c,up)=

Rmax×A(up)−w(up)−totallen. The

other processes in this part remain

the same.

Case 4.3) (totallen + w(up))/A(up) > Rmax,

for this case, we apply the More-R

subroutine; see Fig. 18. In the BUJIO

algorithm,the

weight that node up can bear is

Lmax− w(up).

BUJIO-R algorithm, we must have

L(up)/A(up) ≤ Rmax. Therefore, the

amount of additional edge weight

that up can bear is Rmax× A(up) −

w(up). Thus, we use Rmax× A(up) −

w(up)(instead of Lmax− w(up)) in

line2astheupperboundfortheSPLIT

accumulatededge

However, inthe

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SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING729

TABLE III

COMPARISONS OF THE NUMBERS OF JUMPERS REQUIRED FOR BUJIO, ISPD-05e, DAC-05e, AND ISPD-04e TO FIX ALL ANTENNA VIOLATIONS

BASED ON A ROUTING TREE OF 10000 NODES AND 500 OBSTACLES. NOTE THAT EVEN THOUGH THE RESULTS OF THE ISPD-05e ALGORITHM

IS CLOSE TO OUR BUJIO ALGORITHM, THE BUJIO ALGORITHM CAN ALWAYS FIND THE OPTIMAL SOLUTION WHILE THE ISPD-05e CANNOT;

THIS OPTIMALITY SIGNIFICANTLY DIFFERENTIATES OUR BUJIO ALGORITHM FROM THE PREVIOUS WORK

Fig. 19.

four jumpers on the subtree. Here, Lmax= 200 µm. (d) ISPD-05e algorithm

adds five jumpers on the subtree.

(a) Selected node u. (b) Subtree appended to node u. (c) BUJIO adds

subroutine. The other processes in this

part remain the same.

It is clear from the above discussion that the un-

derlying ideas of Algorithm BUJIO-R are the same

as those of Algorithm BUJIO. Therefore, the opti-

mality proof of Algorithm BUJIO-R for the JIROA-

R problem is similar to that of the BUJIO algorithm.

Furthermore, all the modifications in the BUJIO-

R algorithm do not influence the running time and

the memory requirement. Thus, the time complexity

and the space complexity of the BUJIO-R algorithm

remain the same as BUJIO.

Theorem 4: Algorithm BUJIO-R optimally solves the

JIROA-RprobleminO((V + D)lgD)timeusingO(V )space,

where V is the number of vertices in the given routing tree and

D is the number of obstacles.

VII. EXPERIMENTAL RESULTS

We implemented the BUJIO algorithm in the C++ language

on a 2.4-GHz Intel Pentium PC with 256-MB memory under

the Windows XP operating system.

Since no previous work in the literature considers jumper

insertion on a routing tree with obstacles, we extended the

ISPD-05 work by Wu et al. [9], the DAC-05 work [7] by Su

and Chang, and the ISPD-04 work [3] by Ho et al. to handle

obstacles and made comparisons with our BUJIO algorithm.

For the jumper-insertion algorithms presented at ISPD-05,

DAC-05, and ISPD-04, we just follow their procedures to

insert jumpers. If the position for jumper insertion is in a

forbidden region (an obstacle), we use the same optimal

substitute presented in this paper to insert the jumper. We call

the extended work as ISPD-05e, DAC-05e, and ISPD-04e,

respectively. Moreover, since our BUJIO and the ISPD-05

algorithms are designed for Steiner trees while the DAC-05

and the ISPD-04 ones are for minimum spanning trees, we

generated two sets of different trees based on the same gate

terminals and tested the algorithms on the corresponding trees.

To conduct the experiment, we first generated gate terminals

on grid planes of the dimension 104× 104µm and randomly

placed rectangular obstacles of various sizes on the planes.

Then, we constructed minimal Steiner trees and minimum

spanning trees based on the gate terminals.

Two experiments on the effects of varying Lmaxand varying

node quantity were conducted. To focus on the evaluation of

the existing algorithms, without loss of generality, we assume

that the antenna bound Lmax is measured by wire length.

Table III shows the number of jumpers required for fixing

all antenna violations for a routing tree with 10000 nodes

and 500 obstacles by changing Lmax from 220 to 320 µm.

Column 1 gives the Lmax value, and columns 2, 3, 5, and

7 list the numbers of jumpers required (#J) for fixing the

antenna violations for each Lmaxfor the BUJIO, the ISPO-05e,

the DAC-05e, and the ISPD-04e algorithms, respectively.

Columns 4, 6, and 8 give the percentages of additional jumpers

required (%More) for the respective ISPD-05e, the DAC-05e,

and the ISPD-04e algorithms over BUJIO to fix all antenna

violations,i.e., %More = (#Jumpers of the algorithm −

#Jumpers of BUJIO)/#Jumpers of BUJIO.

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730 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007

TABLE IV

COMPARISONS OF THE NUMBERS OF JUMPERS REQUIRED FOR BUJIO, ISPD-05e, DAC-05e, AND ISPD-04e FOR FIXING ALL ANTENNA VIOLATIONS

BASED ON 11 TEST CASES WITH ROUTING TREES OF 10000 NODES AND 200 OBSTACLES

TABLE V

COMPARISONS OF THE NUMBERS OF JUMPERS REQUIRED FOR BUJIO, ISPD-05e, DAC-05e, AND ISPD-04e FOR FIXING ALL ANTENNA VIOLATIONS

BASED ON 10 TEST CASES WITH ROUTING TREES OF 200 OBSTACLES EACH AND Lmax= 200 µm

It is not surprising that BUJIO requires fewer jumpers than

the ISPD-05e algorithm. However, their difference is not very

significant for this set of test cases. The reason is that the ISPD-

05e algorithm behaves very similarly to BUJIO for this set of

test cases. Only when the gate terminals are adjacent to each

other, the ISPO-05e algorithm adds more jumpers than BUJIO,

as the case shown in Section I. The case is rare for random

designs, and thus, the numbers of jumpers required for the two

algorithms are close. Even though the results of the two algo-

rithms are close, nevertheless, the BUJIO algorithm can always

find the optimal solution while the ISPD-05e cannot; this op-

timality significantly differentiates our BUJIO algorithm from

the previous work. We shall show that BUJIO can significantly

outperform the ISPD-05e one for some nonrandom designs.

It is obvious that BUJIO may need much fewer jumpers

than the DAC-05e and the ISPD-04e algorithms. The reduction

comes from two parts: 1) BUJIO works on Steiner trees while

the DAC-05e and the ISPD-04e algorithms work on minimum

spanning trees. A minimal Steiner tree intrinsically has smaller

wirelength and, thus, needs fewer jumpers to fix the antenna

violations than those of a minimum spanning tree. 2) More

importantly, BUJIO is much more effective than the DAC-05e

and the ISPD-04e algorithms. As shown in Table III, the im-

provements range from 17% to 57%, much more than the 10%

wirelenth difference between the Steiner tree (728568 units

long) and the spanning tree (801302 units long).

The previous experiment shows that the ISPD-05e algorithm

can achieve comparable performance to our BUJIO. In order

to test the robustness of the ISPD-05e algorithm (and the

DAC-05eandISPD-04eones),weconstructedasetoftestcases

based on that shown in Fig. 4. We first generated a test case

of 5000 nodes as usual. After a Steiner tree and a minimum

spanning tree have been constructed, we selected some gate

terminals at the same position in both trees and modified the

selected nodes in the same way. Let node u in Fig. 19(a) be a

selected node. We added a subtree rooted at node u as shown

in Fig. 19(b). The subtree has similar topology as that of the

routing tree shown in Fig. 4. It is clear that BUJIO needs only

four jumpers for the subtree, as shown in Fig. 19(c), while

the ISPD-05e algorithm needs five jumpers, as illustrated in

Fig. 19(d), to fix the antenna violations. We generated the test

cases based on this expansion method.

For the experiments shown in Table IV, we constructed a

corresponding test case for each Lmaxvalue based on the pre-

viously mentioned expansion method. The experimental results

show that BUJIO outperforms the ISPD-05e algorithm by an

average improvement of about 27%. The results reveal that the

ISPD-05e algorithm is not effective for such test cases. Similar

results can be observed from the experiments shown in Table V,

for which we constructed a corresponding test case for each

given number of gate terminals (number of nodes) based on

the aforementioned expansion method. Note that we tested on

larger problem sizes (node numbers) to examine the runtime

differences more closely. For the problems with typical sizes

(node numbers), we conducted another experiment, as shown

in Table VI. The results also show that the BUJIO algorithm

still outperforms the other three algorithms for those practical

problem sizes.

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TABLE VI

COMPARISONS OF THE NUMBERS OF JUMPERS REQUIRED FOR BUJIO, ISPD-05e, DAC-05e, AND ISPD-04e FOR FIXING ALL ANTENNA VIOLATIONS

BASED ON TEST CASES WITH ROUTING TREES OF 200 OBSTACLES EACH

For the experiments shown in Table IV, we constructed a

corresponding test case for each Lmaxvalue based on the pre-

viously mentioned expansion method. The experimental results

show that BUJIO can outperform the ISPD-05e algorithm by an

average improvement of about 27%. The results reveal that the

ISPD-05e algorithm is not effective for such test cases. Similar

results can be observed from the experiments shown in Table V,

for which we constructed a corresponding test case for each

given number of gate terminals (number of nodes) based on the

aforementioned expansion method.

Moreover, the DAC-05e algorithm also outperforms the

ISPD-05e one for the two sets of test cases. The reasons are

twofold: 1) The minimum spanning tree and Steiner tree are the

same for the appended subtrees and 2) the DAC-05e algorithm

adds only four jumpers on each subtree while the ISPD-05e

adds five jumpers. As a result, when the number of the

appended subtrees increases, the DAC-05e algorithm requires

much fewer jumpers than the ISPD-05e one. Therefore, each

of the ISPD-05e and the DAC-05e algorithms has its own

strengths and weaknesses. Each of them might be effective

for some cases but performs poorly for other cases. No matter

what test case is considered, however, BUJIO always finds the

optimal solution.

Table VII shows the CPU times required for antenna fixing

on routing trees of the numbers of nodes ranging from 10000

to 100000, with Lmax= 200 µm and 500 obstacles on each

plane.Column1givesthenumbersofnodesintheroutingtrees.

Because the numbers of nodes are so huge, the program spent

most of the CPU times in reading the input files. Therefore, we

list the CPU times for reading the input files and running the

TABLE VII

COMPARISONS OF THE CPU TIMES REQUIRED FOR BUJIO, ISPD-05e,

DAC-05e, AND ISPD-04e TO FIX THE ANTENNA VIOLATIONS, BASED ON

500 OBSTACLES ON EACH PLANE AND Lmax= 200 µm

algorithms separately in order to examine the time complexity

more closely. The second column (File) gives the CPU times

for reading the input files. The (Main) column in each algorithm

gives the respective CPU times for executing the main body of

the algorithm.

As shown in the table, the empirical running time for the four

methods are close to linear. In particular, BUJIO requires only

1.25stofindanoptimalsolutionforaroutingtreeof0.1million

nodes. Therefore, BUJIO can handle a test case of a very huge

number of nodes in very short time. Fig. 20 shows a layout

resulting from BUJIO with 426 jumpers for antenna fixing on

a routing tree with 1000 nodes and 500 obstacles on the plane

and based on Lmax= 500 µm. Also, Fig. 21 shows a smaller

layout resulting from BUJIO with 197 jumpers for antenna

fixing on a routing tree with 200 nodes and 200 obstacles on

a 2000 × 2000 µm plane and based on Lmax= 100 µm.

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732IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007

Fig. 20.

the obstacles, the circles denote the nodes of the routing tree, the triangles

denote the Steiner points, and the × signs denote the inserted jumpers.

Layout resulting from the BUJIO algorithm. The rectangles denote

Fig. 21.

the obstacles, the circles denote the nodes of the routing tree, the triangles

denote the Steiner points, and the × signs denote the inserted jumpers.

Layout resulting from the BUJIO algorithm. The rectangles denote

VIII. CONCLUDING REMARKS

We have presented an O((V + D)lgD)-time optimal

jumper-insertion algorithm for avoiding/fixing antenna viola-

tions on a Steiner/spanning tree of V nodes with D obstacles.

It is the first optimal algorithm for the general tree-cutting

problem. Empirical results have shown that our algorithms

approach linear and obtain solutions of very high quality. This

paper can be applied to any Steiner/spanning trees (could be a

net to be globally routed or a net after detailed routing) and,

thus, readily be incorporated into a global router for antenna

effect avoidance or a postlayout optimizer for antenna violation

fixing.

Some potential future work includes timing-aware jumper

insertion and integration of jumper insertion and diode insertion

for antenna avoidance/fixing. A jumper consists of two vias and

might incur significant delay. To quantity the timing affected by

jumper insertion, we can incorporate the RC delay of the vias

into the interconnect for overall delay computation.

Jumpers and diodes use different resources—jumpers use

routing resources while diodes consume silicon areas. There-

fore, it might not be easy/accurate to model their tradeoff.

For example, how can we correlate silicon area (mainly for

logic) and routing area (mainly for interconnections) accu-

rately? Nevertheless, they can be considered together to achieve

the best fixing rate of the antenna violations. If there is not

sufficient silicon area for diode insertion, jumpers can be used

to fix antenna violation as long as there is available routing

resource, and vice versa. Therefore, the jumper insertion and

diode insertion problems are usually considered separately by

formulating the routing and silicon resources as constraints. If

wewanttointegratethetwotechniques,however,onewaytodo

so is to correlate the costs (e.g., delay) of vias and diodes (their

extension wires) and optimize the combined cost of jumper and

diode insertion.

REFERENCES

[1] P. H. Chen, S. Malkani, C.-M. Peng, and J. Lin, “Fixing antenna problem

by dynamic diode dropping and jumper insertion,” in Proc. ISQED, 2000,

pp. 275–282.

[2] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to

Algorithms, 2nd ed. New York: McGraw-Hill, 2001.

[3] T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with antenna

avoidance,” in Proc. ISPD, Apr. 2004, pp. 34–40.

[4] S. Krishnan et al., “Assessment of charge-induced damage to ultra-thin

gate MOSFETs,” in Proc. ITEM, 1997, pp. 445–448.

[5] S. Kundu and J. Misra, “A linear tree partitioning algorithm,” SIAM J.

Comput., vol. 6, no. 1, pp. 151–154, Mar. 1977.

[6] H. Shin, C.-C. King, and C. Hu, “Thin oxide damage by plasma etching

and ashing process,” in Proc. IRPS, Mar./Apr. 1992, pp. 37–41.

[7] B.-Y. Su and Y.-W. Chang, “An optimal jumper insertion algorithm for

antenna effect avoidance/fixing,” in Proc. DAC, Jun. 2005, pp. 325–328.

[8] H.Watanabeetal.,“Awaferlevelmonitoringmethodforplasma-charging

damage using antenna PMOSFET test structure,” IEEE Trans. Semicond.

Manuf., vol. 10, no. 2, pp. 228–232, May 1997.

[9] D. Wu, J. Hu, and R. Mahapatra, “Coupling aware timing optimization

and antenna avoidance in layer assignment,” in Proc. ISPD, Apr. 2005,

pp. 20–27.

[10] P. H. Chen, “Beat the competition: A knowledge based design process

addressing the antenna effect and cell placement,” IEEE Circuits Devices

Mag., vol. 20, no. 3, pp. 18–27, Jun. 2004.

Bor-Yiing Su received the B.S. degree in electri-

cal engineering from National Taiwan University,

Taipei, Taiwan, R.O.C., in 2005.

He is currently with the SpringSoft Company in

Taiwan. He plans to conduct graduate study in the

Department of Electrical Engineering at the topmost

universities in America and to obtain a Ph.D. degree

in the area of physical design. His current research

interest is placement-related topics. He is now work-

ing on large-scale congestion driven placement.

Mr. Su was the recipient of the Presidential Award

from National Taiwan University for four semesters during his college years.

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SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING733

Yao-Wen Chang (S’94–M’96) received the B.S.

degree from National Taiwan University, Taipei,

Taiwan, R.O.C., in 1988, and the M.S. and Ph.D.

degrees from the University of Texas at Austin in

1993 and 1996, respectively, all in computer science.

He is a Professor of the Department of Electrical

EngineeringandtheGraduateInstituteofElectronics

Engineering, National Taiwan University. He is cur-

rently also a Visiting Professor at Waseda University,

Kitakyushu, Japan. He was with IBM T. J. Watson

Research Center, Yorktown Heights, NY, in summer

1994. From 1996 to 2001, he was on the faculty of National Chiao Tung

University, Hsinchu, Taiwan. His current research interests lie in VLSI physical

design, design for manufacturing, and FPGA. He has been working closely with

industry on projects in these areas.

Dr. Chang received an award at the 2006 ACM ISPD Placement Contest,

Best Paper Award at ICCD-1995, and eight Best Paper Nominations from

DAC-2007, ISPD-2007, DAC-2005, 2004 ACM TODAES, ASP-DAC-2003,

ICCAD-2002, ICCD-2001, and DAC-2000. He has received many awards

for research performance, such as the 2005 and 2006 First-Class Principal

Investigator Awards and the 2004 Mr. Wu Ta You Memorial Award from the

National Science Council of Taiwan, the 2004 MXIC Young Chair Professor-

ship from the MXIC Corporation, and for excellent teaching from National

Taiwan University and National Chiao Tung University. He is an Editor of

the Journal of Computer and Information Science. He currently serves on the

ACM/SIGDA Physical Design Technical Committee and the technical program

committees of a few important conferences on VLSI design automation,

including ASP-DAC (topic chair), DAC, DATE, FPT, GLSVLSI, ICCAD,

ICCD, ISPD, SOCC, and VLSI-DAT. He is currently the Chair of the Design

Automation and Test (DAT) Consortium of the Ministry of Education, Taiwan,

a member of the Board of Governors of the Taiwan IC Design Society, and a

member of the IEEE Circuits and Systems Society, ACM, and ACM/SIGDA.

Jiang Hu (S’98–M’01) received the B.S. degree

in optical engineering from Zhejiang University,

Hangzhou, China, in 1990, the M.S. degree in

physics from the University of Minnesota, Duluth,

in 1997, and the Ph.D. degree in electrical engineer-

ing from the University of Minnesota, Minneapolis,

in 2001.

He was with IBM Electronics Design Automation

from January 2001 to June 2002. He is currently an

Assistant Professor with the Department of Electri-

cal and Computer Engineering, Texas A&M Uni-

versity, College Station. His research interest is computer-aided design for

very large scale integration circuits and systems, in particular, interconnect

optimization, clock network synthesis, energy efficiency design, and design for

manufacturability.

Dr. Hu was the recipient of the Best Paper Award at the Association

for Computing Machinery (ACM)/IEEE Design Automation Conference in

2001 and an IBM First Plateau Invention Achievement Award in 2003. He

is an Associate Editor of the IEEE TRANSACTIONS ON COMPUTER-AIDED

DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. He has served on the

technical program committees of the Design Automation Conference (DAC),

International Conference on Computer-Aided Design (ICCAD), International

Symposium on Physical Design (ISPD), IEEE/ACM Design, Automation and

Test in Europe (DATE), International Conference on Computer Design (ICCD),

and International Symposium on Circuits And Systems (ISCAS).