An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Impact Factor: 1.2). 05/2007; DOI: 10.1109/TCAD.2007.892338
Source: IEEE Xplore

ABSTRACT We study in this paper the problem of jumper insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-insertion algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our algorithm

  • [Show abstract] [Hide abstract]
    ABSTRACT: Antenna effect is a phenomenon in the plasma-based nanometer process and directly influences the manufacturing yield of VLSI circuits. Because antenna-critical metal wires have sufficient charges to damage the thin gate oxides of the clock input ports connected by a clock tree, the standard cells or IPs cannot be driven by the clock source synchronously. For a given X-architecture clock tree that connects n clock sinks, we consider the antenna effect in the clock tree and propose a discharge-path-based antenna effect detection method. To fix the antenna violations, we use the jumper insertion technique recommended by foundries. Furthermore, we integrate the layer assignment technique to reduce the inserted jumper and via counts. Differing from the existing works, the delay of vias is considered in delay calculation, and a wire sizing technique is applied for clock skew compensation after fixing the antenna violations. Experimental results on benchmarks show that our algorithm runs in O(n2) to averagely insert 48.21% less jumpers and reduce 20.35% in vias compared with other previous algorithms. Moreover, the SPICE simulation further verifies the correctness of the resulting clock tree.
    Integration the VLSI Journal 01/2012; 45:76-90. · 0.53 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper, we propose a jumper insertion algorithm under timing and antenna ratio constraints. Differently from the existing works which assume the jumpers to be placed above the highest layer of a routing tree, our work allows the jumpers to be placed on any routing layer. Furthermore, our algorithm is aware of the delay caused by the jumpers. Experimental results show that, by allowing the jumpers to be placed on any layer, the number of vias added by the jumpers can be reduced by 50%. The experiments also show that our timing-aware jumper insertion algorithm is better at satisfying the timing constraints.
    2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 7-10, 2011; 01/2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: As VLSI technology advances to smaller technology nodes, the antenna effect has become a critical issue in the yield and reliability of the VLSI circuit, especially for analog ICs. Jumper insertion is an effective technique to fix the antenna effect. Traditional works on antenna fixing are mainly for digital ICs rather than analog ICs. This paper presents heuristic algorithms for jumper insertion during routing for analog ICs, which handles the expansion limitation of different types of nets, such as general nets and matching nets, and reexamines the matching parameters of matching nets after jumper insertion. The experimental results show the effectiveness of our algorithms.


Available from