An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles
ABSTRACT We study in this paper the problem of jumper insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-insertion algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our algorithm
Conference Proceeding: Assessment of charge-induced damage to ultra-thin gate MOSFETs[show abstract] [hide abstract]
ABSTRACT: We have devised a novel antenna structure that distinguishes the regimes of charging during an etch process. Using this technique, we show instances in an Inductively Coupled Plasma (ICP) metal etch where charging occurs exclusively during metal clear or overetch or both depending on process and hardware. We have seen instances where ultra-thin gate (21 Å) devices are severely degraded compared to thicker gate (25-32 Å) devices under certain ICP metal etch process conditions. Remote Plasma Nitrided (RPN) oxides are shown to be robust down to 25 Å with respect to antenna effects. We report here for the first time enhanced passivation of plasma damaged device with deuterium annealElectron Devices Meeting, 1997. IEDM '97. Technical Digest., International; 01/1998
Conference Proceeding: Multilevel routing with antenna avoidance.[show abstract] [hide abstract]
ABSTRACT: As technology advances into the nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using a built-in jumper insertion approach. Experimental results show that our approach reduced antenna-violated gates by about 98% and also achieved 100% routing completion for all circuits.Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004; 01/2004
- 01/2001; The MIT Press and McGraw-Hill Book Company., ISBN: 0-262-03293-7
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007719
An Exact Jumper-Insertion Algorithm for Antenna
Violation Avoidance/Fixing Considering
Bor-Yiing Su, Yao-Wen Chang, Member, IEEE, and Jiang Hu, Member, IEEE
Abstract—We study in this paper the problem of jumper in-
sertion on general routing (Steiner/spanning) trees with obstacles
for antenna avoidance/fixing at the routing and/or postlayout
stages. We formulate the jumper insertion for antenna avoidance/
fixing as a tree-cutting problem and present the first optimal
algorithm for the general tree-cutting problem. We show that
the tree-cutting problem exhibits the properties of optimal sub-
structures and greedy choices. With these properties, we present
an O((V + D)lg D)-time optimal jumper-insertion algorithm
that uses the least number of jumpers to avoid/fix the antenna
violations on a Steiner/spanning tree with V vertices and D
obstacles. Experimental results show the superior effectiveness
and efficiency of our algorithm.
Index Terms—Antenna effect, design for manufacturability,
physical design, reliability, routing.
jor concerns in the design and manufacturing of very large scale
integrated circuits. The fine feature size of modern IC tech-
nologies is typically achieved by using plasma-based processes.
In nanometer technology, more stringent process requirements
cause some advanced high-density plasma reactors adopted in
the production lines to achieve fine-line patterns . However,
these plasma-based processes will charge conducting compo-
nents of a fabricated structure. As a result, the accumulated
charges may affect the quality of ICs. This is called the antenna
During metallization, long floating interconnects act as tem-
porary capacitors and accumulate charges gained from the
energy provided by fabrication steps such as plasma etching.
A random discharge of the floating node due to subsequent
process steps could permanently damage transistors in the IC
S PROCESS technology enters the nanometer era, prod-
uct reliability and manufacturing yield have become ma-
Manuscript received May 2, 2006; revised July 19, 2006. The work of
B.-Y. Su and Y.-W. Chang was supported by the National Science Council of
Taiwan, R.O.C., under Grant NSC 93-2815-C-002-046-E, Grant NSC 94-2215-
E-002-005, and Grant NSC 94-2752-E-002-008-PAE. The work of J. Hu was
supported by Semiconductor Research Corporation under Contract 2003-TJ-
1124. This paper was recommended by Guest Editor P. H. Madden.
B.-Y. Su is with the Department of Electrical Engineering, National Taiwan
University, Taipei 106, Taiwan, R.O.C. (e-mail: firstname.lastname@example.org).
Y.-W. Chang is with the Graduate Institute of Electronics Engineering and
also with the Department of Electrical Engineering, National Taiwan Univer-
sity, Taipei 106, Taiwan, R.O.C. (e-mail: email@example.com).
J. Hu is with the Department of Electrical Engineering, Texas A&M Univer-
sity, College Station, TX 77843 USA (e-mail: firstname.lastname@example.org).
Digital Object Identifier 10.1109/TCAD.2007.892338
, . For instance, the exposed polysilicon and metal struc-
tures connected to a thin-oxide transistor will collect charge
from the processing environment (e.g., reactive-ion etching)
and damage the transistor when the discharging current flows
through the thin oxide. The mechanism of antenna damage
is not fully understood, but there is experimental evidence
indicating when charging occurs and how it may affect the
quality of gate oxide , . Charging occurs when conductor
layers, not covered by a shielding layer of oxide, are directly
to this plasma-exposed area. If conductor layers are connected
to a diffusion-layer pattern, such charges are discharged to the
substrate through the diffusion (see Fig. 1 for an illustration).
On the other hand, if the charged conductor layers are con-
nected only to the gate oxide, Fowler–Nordheim tunneling
current through thin oxide discharges such charges and causes
damage to the thin oxide ; see Fig. 1(b) and (c). As shown
in Fig. 1, interconnects are manufactured layer by layer. Before
a conducting path to the diffusion is formed in metal-2-layer
pattern etching [see Fig. 1(d)], the interconnects in the poly and
metal 1 layers might have accumulated so many charges that
they cause damage on the gate in the left of Fig. 1(c) (note that
there will not be any antenna violation after a conducting path
to the diffusion is formed).
The following are popular solutions to reduce the antenna
1) Jumper insertion: Break the signal wires with antenna
violations and route them to the highest layers by jumper
insertion. This reduces the charge amount for violated
wires during manufacturing.
2) Diode insertion: Fix those wires with antenna violations
that have enough rooms for under-the-wire diode (or
reverse diode) insertion. During wafer manufacturing, all
the inserted diodes are floating (or ground). A diode or a
reverse diode can be used to protect all input ports that
are connected to the same output ports.
3) Embedded protection diode: Add protection diodes on
every input port of a standard cell.
4) Antenna-aware routing: Since the antenna effect mainly
occurs in the gate input (with high impedance) and sel-
dom occurs in the diffusion output (with low impedance
and drains out the plasma immediately) for current tech-
nology, an antenna-aware router can try to route the wire
with a high antenna-strength ratio at the diffusion output
and minimize the antenna-strength ratio at the gate input.
0278-0070/$25.00 © 2007 IEEE
720IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007
pattern etching of (a). Charge on the left polypattern is discharged through the
gate while charge on the right polypattern is discharged through the diffusion.
(c) Late stage of metal-1-layer pattern etching of (a). Charge on the left
metal 1 pattern is discharged through the gate while charge on the right
metal 1 pattern is discharged through the diffusion. (d) Late stage of metal-2-
layer pattern etching. Charges on all the metal 2 patterns are discharged through
Antenna effect. (a) Example routing. (b) Late stage of polylayer
Comparing the four methods, for method 3) of embedded
protection diode, since these diodes are embedded and fixed,
they consume unnecessary areas when there is no violation
at the connecting wire. For the second and third methods,
we need extra space in the chip to place the diodes. Because
the number of diodes needed for fixing antenna violations
grows dramatically as the feature shrinks, it is hard to preserve
enough space for diodes in nanometer IC designs. In order
to resolve this problem, the dynamic diode insertion during
the placement with bounding-box-timing estimation is used to
resolve this problem . This functionality is embedded in
many commercial placers. For the fourth method, an already
complex router needs to additionally consider the antenna
effect, and the technique is less effective for fixing the antenna
violations. As a result, jumper insertion becomes one of the
The function of jumper insertion can be explained using Fig. 2.
In Fig. 2(a), when the metal 1 layer is manufactured, the gate
on the right might be damaged because the large area of the
metal 1 interconnection can accumulate sufficient charges to
damage the gate. However, if we insert a jumper to route
the interconnect on the metal 2 layer, as shown in Fig. 2(b),
inserting a jumper from metal 1 layer to metal 2 layer.
Jumper insertion. (a) Stage before inserting a jumper. (b) Stage after
needed for fixing the antenna violation if jumpers can be inserted only beside
tree nodes, as the assumption made in . (b) One jumper suffices to fix the
antenna violation if jumpers can be inserted at an arbitrary position of the wire
segment, as the assumption made in .
Jumper insertion for a wire of 1.3 Lmax long. (a) Two jumpers are
the effective conductor layer becomes smaller. Therefore, the
stored charge is not enough to damage the gate on the right, and
thus, we can avoid the antenna violation.
Although jumper insertion is currently a very popular ap-
proach for antenna avoidance/fixing, jumpers induce vias that
will consume silicon areas and reduce circuit performance.
Therefore, it is desired to fix antenna violations by using the
minimum number of jumpers. The problem of jumper insertion
on a routing tree for antenna avoidance has attracted much
attention in the literature recently. Ho et al. in  propose an
O(V lgV )-time bottom-up approach to insert jumpers in a
spanning tree of V vertices for antenna avoidance. The work
assumes that each tree node corresponds to a gate terminal
and inserts jumpers only beside the tree nodes; its optimality
holds only for this special condition of inserting jumpers right
beside the nodes of a spanning tree. There are two recent works
that consider more general cases for jumper insertion on a
general routing tree (could be a spanning or Steiner tree). The
recent work  relaxes the constraint of inserting jumpers only
beside the tree nodes, for which jumpers can be inserted at an
arbitrary position of a tree edge. The work achieves the same
time complexity as  for the relaxed problem. As an example
shown in Fig. 3, the wire segment is of 1.3 Lmaxlong, where
Lmaxdenotes the upper bound for antenna (i.e., any wire longer
than Lmaxwill violate the antenna rule). For this wire segment,
the work in  needs two jumpers to fix the antenna violation
[see Fig. 3(a)] while a single jumper suffices for the work  to
fix the violation [see Fig. 3(b)].
SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING721
jumpers c1,...,c4to solve the antenna violations. (c) This paper needs only
three jumpers c5, c6, and c7to satisfy the antenna rule.
(a) Routing tree with two sink nodes u1and u2. (b) Work in  needs
Another recent work  by Wu et al. extends the work in 
to handle either a spanning or a Steiner tree. With the imple-
mentation scheme proposed by Kundu and Misra , the work
a Steiner/spanning tree for antenna avoidance/fixing. To fix the
antenna violation of a sink node (a gate terminal in this paper),
the work first removes all subtrees around the node that violate
the antenna rules. After all such subtrees are removed, if the
sink still violates the antenna rule, the work will continually
remove the heaviest branch from the sink until the antenna rules
For the case with two adjacent sink nodes, their method might
not be optimal. As the routing-tree example shown in Fig. 4(a),
u1and u2are two sink nodes, the number beside each edge
denotes the antenna charge weight (measured by the ratio of
antenna strength (length, area, perimeter, etc.) to the gate size,
antenna weight that a sink node can bear is assumed to be ten.
For the work in , since we cannot partition the tree into
any subtree with the total weight equal to ten, we will cut
the heaviest edge near the sink node until the antenna rule is
satisfied on u1and u2. Thus, the edge e(u1,u2) = 10 will be
removed first, and the work will insert four jumpers c1, c2, c3,
and c4, as shown in Fig. 4(b). Nevertheless, for this case, three
jumpers suffice to solve the antenna violations; see the jumpers
c1, c2, and c3shown in Fig. 4(c).
For a jumper-insertion algorithm to be practical, we shall
work on general routing (Steiner or spanning) trees, in which
a tree node represents a gate terminal and a Steiner node
represents a routing junction. We shall also allow a jumper
FEATURES OF THE RELATED JUMPER INSERTION WORKS
to be inserted at an arbitrary position of a tree edge. Since
jumper insertion routes a signal wire to the top most layer, we
must further consider the routing with obstacles in the active
layers—the layers from the current routing layer up to the
top most layer, which could be prerouted nets, power/ground
nets, clock nets, etc. A jumper-insertion algorithm that does
not work on Steiner trees, allow arbitrary jumper-insertion
position, or consider routing obstacles cannot be practical for
In this paper, we consider the general case of inserting
jumpers at arbitrary positions of tree edges with obstacles for
antenna avoidance/fixing (see Table I for the features consid-
ered by the recent jumper-insertion algorithms). We formulate
the general jumper insertion for antenna avoidance (applicable
at the routing stage) and/or fixing (applicable at the postlayout
stage) with obstacles as a tree-cutting problem on a Stenier/
spanning tree and present the first optimal algorithm for the
general tree-cutting problem. We show that the tree-cutting
problem exhibits the properties of optimal substructures and
greedy choices. With these properties, a greedy algorithm
suffices to find an optimal solution . Based on the theory,
we present an O((V + D)lgD)-time optimal jumper-insertion
algorithm that uses the minimum number of jumpers to fix the
antenna violations in a Steiner/spanning tree with V vertices
and D obstacles. Experimental results show that our algorithm
is very efficient and effective.
The remainder of this paper is organized as follows.
Section II formulates the problem of jumper insertion on a
Steiner/spanning tree with obstacles for antenna avoidance/
fixing. Section III presents an optimal algorithm for the
proposed problem. Section IV proves the optimality of the
algorithm. Section V analyzes the complexity of the algo-
rithm. Section VI extends the algorithm to the handling of
the antenna-strength-to-gate-size model. Section VII reports
the experimental results. Finally, the conclusions are given
in Section VIII.
II. PROBLEM DEFINITION
Before formulating our problem, we first list the notation
used in this paper in Table II for clarity.
To avoid/fix the antenna violation, we require that the to-
tal effective conductor connecting to a gate be less than or
equal to a threshold Lmax. The threshold could be the ratio
of antenna strength (length, area, perimeter, etc.) to the gate
size, wire-area limit, wire-perimeter limit, wire-length limit,
or any model of the strength of antenna effect caused by
conductors. For example, for wire area, we can simply compute
the product of the wire length and the wire width (size); for the
722IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007
NOTATION USED IN THE ALGORITHM
accumulated on edges e(u,s), e(s,v1), and e(s,v2) will all cause antenna
effect on u.
u, v1, and v2are gate terminals, and s is a Steiner point. The charges
antenna-strength-to-gate-size ratio, we can simply model the
antenna strength divided by the gate size as the edge weight.
It will be clear later in Section VI that the modeling of the
antenna-strength-to-gate-size ratio is still feasible, since our ap-
proach processes gate by gate for the antenna avoidance/fixing.
Typically, a net is modeled as a routing tree, where a node in
the tree denotes a circuit terminal/junction (a gate, diffusion,
or junction of interconnects) and an edge denotes the inter-
connection between two circuit terminals or junctions. Since
the interconnection connecting to a diffusion terminal will not
cause any antenna violation, as explained in Section I, we shall
focus on those connecting to gate terminals.
Let T = (V = VG∪ VN,E) be a Steiner tree. The set VG
of the nodes represents all gate terminals, the set VN of the
nodes represents all Steiner points, the set E of the edges
denotes the wires connecting the circuit terminals or junctions,
and an edge weight gives the measure of the wires with the
same unit as Lmax. Note that a Steiner point denotes a wire
junction, which cannot help discharge the wire (see Fig. 5
for an illustration). The charges accumulated on edges e(u,s),
e(s,v1), and e(s,v2) will all cause antenna effect on the gate
terminal u (we shall focus on Steiner trees in the following
discussions; the proposed method readily applies to spanning
trees, for which VN= ∅).
For example, if Lmaxis a wire-length limit, an edge weight
If Lmax is a wire-area limit, the edge weight denotes the
wire area (and so is the ratio of antenna strength to the gate
size). A gate will violate the antenna rule if the effective
conductor incident on the gate (i.e., the effective weight—the
sum of the weights of the edges incident on the corresponding
node) is larger than Lmax. To reduce the antenna effects on
are cutting nodes. Therefore, the sum of effective edge weights of u1, u2, and
u3are: L(u1) = l(u1,u2) + l(u1,c1) + l(u1,s1) + l(s1,u3) + l(s1,c2),
L(u2) = l(u1,u2), L(u3) = l(u1,s1) + l(s1,u3) + l(s1,c2).
u1, u2, and u3are gate terminals. s1is a Steiner point. c1and c2
a gate, we can apply the technique illustrated in Fig. 2 by
adding a jumper on a wire connecting to the gate to reduce
the effective conductor. This operation is modeled as adding
a cutting node on the tree edge corresponding to the wire to
reduce the effective edge weight associated with the gate node.
As aforementioned, jumpers are implemented by vias, which
will consume silicon areas and reduce circuit performance.
Therefore, it is desired to fix antenna violations by using the
minimum number of jumpers. In other words, given a routing
tree (V = VG∪ VN,E) and an upper bound on the antenna
Lmax, we intend to add the minimum number of cutting nodes
on the tree edges so that the effective edge weight associated
with each node is smaller than Lmax. Let p(u) denote the
node u’s parent. Let L(u) denote the sum of the effective edge
weights (strength ratio, wire lengths, wire areas, wire perimeter,
etc.) on node u (see Fig. 6 as an illustration). Let D be the set
of obstacles in the active layers (for simplicity, we focus our
discussions on the rectangular obstacles; the jumper-insertion
algorithm to be presented in this paper readily applies to the
problem with obstacles of arbitrary shapes, with additional
procedures for obstacle identification). The projection of the
obstacles in D defines the forbidden regions for the edges and
nodes of a routing tree for jumper insertion. Let F be the
set of the forbidden regions. Given a node u (an edge or a
tree segment e) of a routing tree, f(u) = 1 (f(e) = 1) if the
node u (the edge/segment e) falls inside the forbidden regions
(u ∈ F); f(u) = 0 (f(e) = 0), otherwise. With the definitions
above, we can formulate the addressed problem as follows.
Problem Jumper Insertion on a Routing tree with Obstacles
for Antenna (JIROA) avoidance/fixing: Given a routing tree
T = (V = VG∪ VN,E), an upper bound Lmax, and a set D of
rectangular obstacles, find the minimum set C of cutting nodes
on edges c ?= u for any c ∈ C and u ∈ V and f(c) = 0 for any
c ∈ C, so that L(u) ≤ Lmax, ∀u ∈ VG.
Note that the routing tree in this formulation represents a net
in any layout design stage, e.g., a net to be globally routed, a net
after detailed routing (in the postlayout stage). Therefore, the
JIROA problem is applicable to the antenna estimation in the
global/detailed routing stage and the antenna violation fixing in
the postlayout stage.
III. ALGORITHM FOR FINDING THE MINIMUM |C|
For the JIROA problem, we present in this section an
O((V + D)lgD)-time optimal algorithm, named Bottom Up
Jumper Insertion with Obstacles (BUJIO), for finding the mini-
mum cutting set C for a given routing (Steiner or spanning) tree
T = (V,E) with V nodes and D obstacles (note that we use V
to denote the set or the number of nodes in a routing tree, which
SU et al.: EXACT JUMPER-INSERTION ALGORITHM FOR ANTENNA VIOLATION AVOIDANCE/FIXING723
Subroutines EqualLess and More to deal with the subleaf nodes.
Algorithm BUJIO deals with the leaf nodes first and, then, call
Illustration of the r(u,v) function, where c is just beside the forbidden
is common in the community of computer science; its meaning
is clear from the context). Algorithm BUJIO is summarized
in Fig. 7.
Let l(e) (or l(u,v)) be the weight (could be the strength ratio,
wire length, wire area, wire perimeter, etc.) of the edge e =
(u,v) in T. In the BUJIO algorithm, we add the cutting nodes
into the original tree in a bottom-up manner. We first define a
subleaf node and an optimal replacement function r(u,v) (see
Fig. 8 for an illustration) as follows.
Definition 1: A subleaf is a node for which all its children
are leaf nodes, and if any of its children is a gate terminal, the
edges between it and its children all have weights ≤ Lmax.
Definition 2: Let u and v be two adjacent nodes with
f(v) = 1. Then, r(u,v) denotes the cutting node c on edge
e = (u,v) with f(c) = 0 and l(u,c) being the maximum
in an obstacle (denoted by the shaded region), where d1,d2,...,d5 are
nodes on the tree edges, just beside the obstacle. (b) Reducing the tree of
(a) by removing edges e(u,d1),e(u,d2),...,e(u,d5) and assigning w(u) =
Example reduction for Step 2). (a) Routing tree with a node u
among every node on edge e(u,v). In other words, c is just
beside the forbidden region covering node v (see Fig. 8).
We derive the BUJIO algorithm based on the following
Step 1) Line 1 of Algorithm BUJIO: Sort the obstacles in D
by the x-axes and then the y-axes.
With this process, we can determine f(u) and f(e)
in O(lgD) time.
Step 2) Lines 2–4 of Algorithm BUJIO: We compute the
weight of every node.
If a tree node u ∈ V is in a forbidden region, some
segments of the edges incident on u could also
be in the forbidden region. Therefore, we cannot
insert jumpers on these segments, and charges in-
duced from these segments cannot be removed. We
use weight w(u) to record such information. That
is, w(u) =?
w(u) > Lmax for some node u, the accumulated
charges on u are over the upper bound that u can
tolerate. For this case, we cannot prevent node u
from antenna violation by jumper insertion alone.
Otherwise, we can always find an optimal solution
for jumper insertion. For the feasible case of a set
of edges incident on a node u, we can reduce the
problem with obstacles into the case without any ob-
inside the obstacles to node u and assigning w(u) =
processing, we can insert jumpers just as the case
without any obstacles.
Step 3) Lines6–15ofAlgorithmBUJIO:Wedealwithevery
In this step, our main goal is to prevent every leaf
node from antenna violation. Obviously, if we have
dealt with a leaf node, we need not consider it
any more. Therefore, line 7 of the BUJIO algo-
rithm marks these nodes to make sure that every
leaf node is processed only once. If l(u,p(u)) +
w(u) ≤ Lmax, the leaf node u satisfies the antenna
f(e)=1∧eincidentonul(e). Obviously, if
i=1l(ei) (see Fig. 9 for an illustration). After this