Article

Design-Intent Coverage—A New Paradigm for Formal Property Verification

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (impact factor: 1.27). 11/2006; DOI:10.1109/TCAD.2005.859490 pp.1922 - 1934
Source: IEEE Xplore

ABSTRACT It is essential to formally ascertain whether the register-transfer level (RTL) validation effort effectively guarantees the correctness with respect to the design's architectural intent. The design's architectural intent can be expressed in formal properties. However, due to the capacity limitations of formal verification, these architectural properties cannot be directly verified on the RTL. As a result, a set of lower level RTL properties are developed and verified against the RTL modules. In a top-down design approach, the architect would ideally like to formally guarantee the coverage of the architectural intent at the time of creating the specifications for the component RTL modules (that is, before they are passed to the designers for implementation). In this paper, the authors present: 1) a method for checking whether the RTL properties are covering the architectural properties, that is, whether verifying the RTL properties guarantees the correctness of the design's architectural intent; 2) a method to identify which architectural properties are still uncovered, that is, not guaranteed by the RTL properties; and 3) a methodology for representing the gap between the specifications in a legible form

0 0
 · 
0 Bookmarks
 · 
24 Views
  • Source
    Conference Proceeding: Orchestrated multi-level information flow analysis to understand SoCs
    G. Fey
    [show abstract] [hide abstract]
    ABSTRACT: Complex Systems on Chip are developed by large design teams integrating various different blocks. Typically, no single person in the design team understands all details of such a design. Integrating new designers into the team as well as debugging failures or performance problems becomes a time-consuming cost-generating threat to the overall project. We envision tool support for these critical steps. The paths of information flow are automatically extracted and explanations for certain behavior are derived by reasoning engines. Then, the designer interactively explores the design within this environment.
    Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE; 07/2011
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.

Keywords

architectural intent
 
architectural properties
 
authors present
 
component RTL modules
 
correctness
 
design's architectural intent
 
designers
 
formal properties
 
formal verification
 
lower level RTL properties
 
register-transfer level
 
RTL
 
RTL modules
 
RTL properties
 
RTL properties guarantees
 
specifications
 
top-down design approach
 
verifying
 

P Basu