Test data compression based on input-output dependence
ABSTRACT We use the fact that outputs of a large circuit depend on proper subsets of the circuit inputs to provide test data compression on the input side. The compressed input test data consists of patterns of length equal to the maximum number of inputs on which an output depends. This is typically smaller than the number of circuit inputs. A distribution block expands every input pattern into several test patterns for the circuit, one test pattern for every input pattern and input subset. We present experimental results to show that significant compression can be achieved by the proposed approach while maintaining complete fault coverage.
- IEEE Trans. on CAD of Integrated Circuits and Systems. 01/1995; 14:1496-1504.
Conference Proceeding: Two-dimensional test data compression for scan-based deterministicBIST[show abstract] [hide abstract]
ABSTRACT: A novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional compression scheme, which combines the advantages of known vertical and horizontal compression techniques. To reduce both the number of patterns to be stored and the number of bits to be stored for each pattern, deterministic test cubes are encoded as seeds of an LFSR (horizontal compression), and the seeds are again compressed into seeds of a folding counter sequence (vertical compression). The proposed BIST architecture is fully compatible with standard scan design, simple and flexible, so that sharing between several logic cores is possible. Experimental results show that the proposed scheme requires less test data storage than previously published approaches providing the same flexibility and scan compatibilityTest Conference, 2001. Proceedings. International; 02/2001
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ABSTRACT: A compression/decompression scheme based on statistical coding is presented for reducing the amount of test data that must be stored on a tester and transferred to each core in a core-based design. The test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core. Given the set of test vectors for a core, a statistical code is carefully selected so that it satisfies certain properties. These properties guarantee that it can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) which requires very small area. Results indicate that the proposed scheme can use a simple decoder to provide test data compression near that of an optimal Huffman code. The compression results in a two-fold advantage since both test storage and test time are reduced. 1. Introduction One of the increasingly difficult challenges in testing systems-on-a-chip is dea...03/1999;