Toward Ideal On-Chip Communication Using Express Virtual Channels

Princeton Univ., Princeton
IEEE Micro (Impact Factor: 2.39). 02/2008; DOI: 10.1109/MM.2008.18
Source: DBLP

ABSTRACT Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. we propose reducing energy and delay, and increasing throughput, using express virtual channels. packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.

  • [Show abstract] [Hide abstract]
    ABSTRACT: The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon NanoTube (CNT) antennas are shown to outperform traditional wire-based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies will be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This article advocates adoption of such complex network-based architectures to minimize the effect of wireless link failures on the performance of the NoC. Through cycle-accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of high degrees of link failures. We demonstrate the robustness of the proposed wireless NoC architecture by incorporating both uniform and application-specific traffic patterns.
    ACM Journal on Emerging Technologies in Computing Systems (JETC). 09/2013; 9(3).
  • [Show abstract] [Hide abstract]
    ABSTRACT: We consider a way to build distributed full switches of an arbitrary size, consisting of small fixed-size switches and channel splitters. The distributed switch preserves the nonblocking and self-routing properties of a full switch and forms an ideal system area network.
    Automation and Remote Control 04/2013; 74(4). · 0.19 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Current commercial systems-on-chips (SoCs) designs integrate an increasingly large number of predesigned cores and their number is predicted to increase significantly in the near future. For example, molecular-scale computing promises single or even multiple order-of-magnitude improvements in device densities. The network-on-chip (NoC) is an enabling technology for integration of large numbers of embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of long multi-hop links used in data exchange. The latency, power consumption and interconnect routing problems of conventional NoCs can be addressed by replacing or augmenting multi-hop wired paths with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the design of wireless NoCs (WiNoCs) with on-chip antennas, suitable transceivers and routers. Moreover, as it is an emerging technology, the on-chip wireless links also need to overcome significant challenges pertaining to reliable integration. In this paper, we present various challenges and emerging solutions regarding the design of an efficient and reliable WiNoC architecture.
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems - JETCAS. 01/2012; 2(2):228-239.


Available from