Cognitive radios for dynamic spectrum access - polyphase multipath radio circuits for dynamic spectrum access

Twente Univ., Enschede
IEEE Communications Magazine (Impact Factor: 3.66). 06/2007; DOI:10.1109/MCOM.2007.358856
Source: IEEE Xplore

ABSTRACT Dynamic access of unused spectrum via a cognitive radio asks for flexible radio circuits that can work at an arbitrary radio frequency. This article reviews techniques to realize radios without resorting to frequency selective dedicated filters. In particular, a recently proposed polyphase multipath technique canceling harmonics and sidebands is discussed. Using this technique, a wideband and flexible power upconverter with a clean output spectrum has been realized on a CMOS chip, aiming at flexible radio transmitter application. Prototype chips can transmit at an arbitrary frequency between DC and 2.4 GHz. Unwanted harmonics and sidebands are more than 40 dB lower than the desired signal up to the 17th harmonic of the transmit frequency

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    IEEE Trans. on Circuits and Systems. 01/2011; 58-I:253-263.
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    ABSTRACT: Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.
    International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil; 01/2011
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    ABSTRACT: Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5 p<sub>rms</sub><sup>s</sup> clock jitter. In comparison, existing architectures based on time-interleaving require 0.5 p<sub>rms</sub><sup>s</sup> clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband-communication-receiver development and provides the potential to enable several high-data-rate communication applications.
    Circuits and Systems I: Regular Papers, IEEE Transactions on 03/2011; · 2.24 Impact Factor

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