Article

A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs

Los Alamos Nat. Lab., Los Alamos
IEEE Transactions on Nuclear Science (Impact Factor: 1.46). 01/2008; DOI: 10.1109/TNS.2007.910871
Source: IEEE Xplore

ABSTRACT With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) is a common fault mitigation technique for FPGAs and has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. This paper evaluates three additional mitigation techniques and compares them to TMR. These include quadded logic, state machine encoding, and temporal redundancy, all well-known techniques in custom circuit technologies. Each of these techniques are compared to TMR in both area cost and fault tolerance. The results from this paper suggest that none of these techniques provides greater reliability and often require more resources than TMR.

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    • "The technique is widely used in mission-critical applications for fault detection as well as fault masking. As mentioned previously, TMR [13], [14] configuration involves three replicas of the design which are running at a time and the outputs are compared by a voting element. The majority voted output is passed through and becomes the actual output of the system. "
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    • "Also, the TMRed design has more than three times the LUTs of the original design with the addition of the voter circuits used to mask out the erroneous output values of the triplicate circuits. Taking into account the experiments in [5] [6] [7] [8] [9] and our experiments, we estimate that the overhead in LUTs by TMR may be from 3.2 times to 3.9 times. "
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