Article

Single Event Effects in High Density CMOS SRAMs

NTT Electrical Communications Laboratories 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa, 243-01 Japan
IEEE Transactions on Nuclear Science (impact factor: 1.45). 01/1987; DOI:10.1109/TNS.1986.4334654 pp.1632 - 1636
Source: IEEE Xplore

ABSTRACT The effects of epi-substrate and a cell power supply layout on heavy-ion induced latch-up for 64K SRAMs are examined by heavy-ion exposure tests using a cyclotron. It is shown that epi-substrate alone is not sufficient to prevent latch-up. A cell power supply layout technique, that is, power is supplied through the well for MOSFETs in the well, combined with epi-substrate is very effective in preventing latch-up for high density CMOS/BULK memories. Soft error cross sections and threshold LETs for various CMOS SRAMs are determined by heavy-ion exposure tests. The threshold LET for conventional 64K SRAMs decreases to about one-fifth that of 1K SRAMs.

0 0
 · 
1 Bookmark
 · 
31 Views
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.

Keywords

1K SRAMs
 
64K SRAMs
 
cell power supply layout
 
cell power supply layout technique
 
conventional 64K SRAMs decreases
 
cyclotron
 
density CMOS/BULK memories
 
epi-substrate
 
heavy-ion exposure tests
 
heavy-ion induced latch-up
 
latch-up
 
Soft error
 
threshold LET
 
threshold LETs
 
various CMOS SRAMs