Characterization of spiral inductors with patterned floating structures
ABSTRACT The impact of two different types of floating patterns on spiral inductors was investigated. Both patterned trench isolation with a floating p/n junction and floating metal poles were implemented underneath reference spiral inductors. All three types of inductors have an identical spiral geometry. Combination of patterned trench isolation with a floating p/n junction increases maximum quality factor (Qmax) by 17% compared to the reference inductors. The floating metal poles enable adjustment of the frequency at Qmax (fmax) without hampering the Qmax. A ladder-type lump-element model was employed to analyze inductor performance after it was demonstrated to precisely capture behavior of all three inductors. Enhancement of the quality factor due to patterned trench isolation with a floating p/n junction was found to result from an increment of effective resistivity in substrates. Reduction of the frequency fmax due to the floating metal poles was caused by increasing effective coupling capacitance between the spiral inductors and substrate.
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ABSTRACT: Spiral inductors and different types of transmission lines are fabricated by using copper (Cu)-damascene interconnects and high-resistivity silicon (HRS) or sapphire substrates. The fabrication process is compatible with the concepts of silicon device fabrication. Spiral inductors with 1.4-nH inductance have quality factors (Q) of 30 at 5.2 GHz and 40 at 5.8 GHz for the HRS and the sapphire substrates, respectively. 80-nH inductors have Q's as high as 13. The transmission-line losses are near 4 dB/cm at 10 GHz for microstrips, inverted microstrips, and coplanar lines, which are sufficiently small for maximum line lengths within typical silicon-chip areas. This paper shows that inductors with high Q's for lumped-element designs in the 1-10-GHz range and transmission lines with low losses for distributed-element designs beyond 10 GHz can be made available with the proposed adjustments to commercial silicon technologyIEEE Transactions on Microwave Theory and Techniques 11/1997; · 2.23 Impact Factor
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ABSTRACT: A silicon micromachining method has been developed to fabricate on-chip high-performance suspended spiral inductors. The spiral structure of an inductor was formed with polysilicon and was suspended over a 30-μm-deep cavity in the silicon substrate beneath. Copper (Cu) was electrolessly plated onto the polysilicon spiral to achieve low resistance. The Cu plating process also metallized the inner surfaces of the cavity, forming both a good radio-frequency (RF) ground and an electromagnetic shield. High quality factors (Qs) over 30 and self-resonant frequencies higher than 10 GHz have been achieved. A study of the mechanical properties of the suspended inductors indicates that they can withstand large shock and vibration. Simulation predicts a reduction of an order of magnitude in the mutual inductance of two adjacent inductors with the 30-μm-deep Cu-lined cavity from that with silicon as the substrate. This indicates very small crosstalk between the inductors due to the shielding effect of the cavitiesIEEE Transactions on Microwave Theory and Techniques 01/2001; · 2.23 Impact Factor
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ABSTRACT: This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 μm SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-Turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH/μm<sup>2</sup> is obtained for a 42 nH MTS (Multi-Turn, multiple metal layers in Series) inductor.Radio Frequency Integrated Circuits (RFIC) Symposium, 2003 IEEE; 07/2003