HiperLAN 5.4-GHz low-power CMOS synchronous oscillator
ABSTRACT A 5.4-GHz 0.25-μm very-large-scale-integration CMOS synchronous
oscillator (SO) is proposed in this paper, which is designed to act as a
local oscillator for HiperLAN systems. The advantage of using such an
oscillator in a double-loop frequency synthesizer is demonstrated. The
design strategy leading to an optimized SO with regards to its
synchronization range is described. A test chip is presented, which
provides a 150-MHz synchronization range and a -97-dBc/Hz phase noise at
10-kHz offset from the 5-GHz carrier, while consuming only 5 mA from a
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- "The injection-locking bandwidth can approximately be found from (1) by fitting it to a first-order transfer function. It is worth noting that a more rigorous analysis similar to other works (e.g., , ) can be applied to a PILO to investigate its open-loop injection-locking properties. Equation (2) reveals that the relative change in tank voltage, and thus the injection strength, increases by increasing the pulse width, or decreasing the switch resistance. "
ABSTRACT: This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mum integrated circuit with active area of 0.4 mm<sup>2</sup> and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), -63.9 dBc, and 200 fs (peak-to-peak), respectively.IEEE Journal of Solid-State Circuits 06/2009; 44(5-44):1391 - 1400. DOI:10.1109/JSSC.2009.2015816 · 3.01 Impact Factor
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- "Frequency multiplication is an important function in frequency synthesis, clock distribution, and a wide range of RF and microwave applications. The combination of a VCO with a frequency multiplier can enable the VCO to work at lower frequency –, which can be designed with better spectral purity. This arrangement can also avoid a VCO pulling problem and allow a lower frequency synthesizer division radio. "
ABSTRACT: This paper proposes a variable-modulus injection-locked frequency multiplier for better harmonic suppression. It is more suitable for fully-integrated implementation using low-Q on-chip inductors in digital CMOS than conventional approaches. A prototype dual-modulus frequency doubler/tripler with 1.6 GHz input and 3.2 GHz/4.8 GHz output is implemented in a 0.18 mum standard digital CMOS. At 5% locking range, the doubler mode achieves fundamental suppression of 42 dB with 2.2 mW power consumption from 1 V supply; while the tripler mode achieves 40 dB suppression at the fundamental and 32 dB at the second harmonic, with 3.7 mWpower consumption from 1 V supply. Good phase noise performance is achieved for both doubler and tripler modes.Radio Frequency Integrated Circuits Symposium, 2008. RFIC 2008. IEEE; 01/2008
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ABSTRACT: Thesis (Ph. D.)--University of Rochester. Dept. of Electrical and Computer Engineering, 2010. The generation and distribution of high speed and high quality clock signals have become increasingly important in high performance microprocessors, wireline communications and wireless communications. In multi-gigahertz frequency range, conventional clocking techniques have encountered several design challenges in terms of power consumption, skew and jitter. Injection-locking is a promising technique to address these design challenges for gigahertz clocking. This dissertation presents our studies of gigahertz, high performance, low power clock generation and distribution using injection-locked frequency dividers (ILFDs), injection-locked frequency multipliers (ILFMs) and injection-locked clock distribution networks (ILCs). Chip prototypes in 0:18μm standard digital CMOS technologies are demonstrated for the following gigahertz clocking circuits. For gigahertz clock generation, we introduced a phase tuning scheme for an ILFDbased dual-phase signal generator. The phase tuning capability in this scheme comes from the tunable phase transfer characteristics of injection-locked frequency dividers. Implemented with a frequency-tunable double-balanced divide-by-two injection-locked frequency divider, the dual-phase signal generator prototype achieves 100o dierential phase tuning range around quadrature with generated signal frequency of 5 GHz. For gigahertz frequency division, we introduced a divide-by-odd-number injectionlocked frequency divider to address the division ratio limitation of conventional injectionlocked frequency dividers. With dierential injection and harmonic ltering, this new ILFD topology maintains the fully dierential nature of the output signal, while at the same time achieving eective mixing between the injected odd harmonics and output oscillation. 5% locking range without frequency tuning is achieved for the circuit prototype of this topology working at input frequency of 16-18 GHz. For gigahertz frequency multiplication, we introduced an injection-locked oscillator to work as a high-gain, high-Q harmonic lter for conventional harmonicgeneration- and-ltering frequency multipliers. This new approach achieves significantly better undesired harmonic suppression for frequency multipliers built with lossy digital CMOS processes. Frequency tunability of injection-locked oscillators also enables multi-mode operations for such injection-locked frequency multipliers. The circuit prototype of such a frequency multiplier achieves multiply by 2 and 3 dualmode operation with undesired harmonic suppressions better than 30 dB achieved for both modes. For gigahertz clock distribution, we proposed an injection-locked clocking scheme using injection-locked oscillators (ILOs) as the local clock regenerators. Because of an ILO's capability to be locked by a small input signal, this new approach reduced a large amount of clock buers in global clock distribution. This not only reduces the power consumption, but also reduces the skew and jitter which come from these clock buers. The phase tunability of ILOs can also be utilized to achieve the deskew function between dierent clock domains. Three circuit prototypes of ILCs working at several gigahertz have been built. They demonstrated better power and jitter performance together with the built-in deskew capability of ILCs.