Measuring the timing jitter of ATE in the frequency domain
ABSTRACT The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.
- [Show abstract] [Hide abstract]
ABSTRACT: Nowadays some microcontroller clock circuits have been implemented using relaxation oscillators instead of quartz type approach to attend cost effective designs. The oscillator is compensated over temperature and power supply and trimming during device test phase adjusts the oscillation frequency on target to overcome process variations. In that way, the relaxation oscillator becomes competitive with regard to ceramic resonator options. However, robust applications as industrial, automotive and aero spatial, requires aggressive EMC tests reproducing the behavior in these environments. High levels of RF interference introduce frequency deviation, jitter or clock corruption causing severe faults on the application. This work discusses the impact of RF interference in relaxation oscillators proposing a strategy to implement test mode in microcontrollers and other complex SOCs, allowing yet characterization and fault debug. Theoretical analysis and experimental results with a silicon implementation are presented and discussed.01/2010;
- [Show abstract] [Hide abstract]
ABSTRACT: Crystal oscillators are usually implemented using Pierces configuration due to its high stability, small amount of components, and easy adjustment. With technology development and device shrinking, modern microcontroller embedded oscillators include all network components integrated on chip to attend cost-effective designs supporting both crystals and ceramic resonators. This fact makes the oscillator more sensitive to feedback network load and strays related to the ESD protections required at the external crystal I/O pins. Robust applications such as industrial, automotive, biomedical, and aerospace require aggressive EMC qualification tests where high power RF interference is injected causing jitter, frequency deviation, or even clock corruption that traduces in severe faults at system level. This work discusses the impact of RF interference on crystal oscillators. A theoretical load factor analysis is proposed and compared to experimental results obtained from a 0.35μm CMOS silicon test vehicle. Finally, a test strategy for microcontrollers and complex SoCs is presented.01/2011;
sor, pattern generator, and timing generator (TG)]; in the last
The remaining sections are organized as follows. Section II 75
discusses the basic issues associated with signal integrity re- 76
volving around dc–dc converters. Furthermore, it introduces 77
an analytical model for jitter that is amenable to a frequency- 78
domain-measurement approach. A methodology for measuring 79
the jitter due to radiated EMI is then proposed in Section III, 80
followed by experimental results in Section IV. Finally, con- 81
clusions are drawn in Section V.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 20061
Measuring the Timing Jitter of ATE
in the Frequency Domain
Luca Schiano, Student Member, IEEE, Mariam Momenzadeh, Student Member, IEEE,
Fengming Zhang, Young Jun Lee, Student Member, IEEE, Thomas Kane, Member, IEEE,
Solomon Max, Life Senior Member, IEEE, Philip Perkins, Member, IEEE,
Yong-Bin Kim, Senior Member, IEEE, Fabrizio Lombardi, Senior Member, IEEE,
and Fred Jackie Meyer, Member, IEEE
Abstract—The objective of this paper is to provide a framework
by which jitter, in the output signals of a test-head board in an
automatic test equipment (ATE), can be measured. In this paper,
jitter phenomena caused by radiated electromagnetic interference
(EMI) noise are considered. EMI noise is mainly present in the test
head of an ATE as result of the activity of the dc–dc converters.
An analysis has been pursued to establish the areas of the
test-head board that are most sensitive to EMI noise. The most
sensitive part of the test-head board has been found to occur
in the loop filter of the phase-locked loop (PLL) that is used
to obtain a high-frequency clock for the timing generator (TG).
Different H-fields are then externally applied to the loop filter to
verify the behavior of the output signal in terms of rms jitter.
A frequency-domain methodology has been employed for the
rms-jitter measurements. The rms-jitter variation for the radiated
EMI magnitude and frequency has been characterized. Also, the
orientation of the external H-field source has been investigated
with respect to the target board and its effects on the measured
rms jitter. For measuring the jitter, an interface circuitry has been
designed on an adapter board to circumvent ground noise and
connectivity problems arising from the test-head environment.
Index Terms—Automatic test equipment, electromagnetic-
interference (EMI)-induced jitter, frequency domain, jitter char-
acterization, jitter measurement, test-head board.
I. INTRODUCTION 32
tectures have undergone radical changes in operation and de-
sign . Past ATE architectures were based on shared resources
[i.e., all channels share components such as the test proces-
O MEET the challenge of designing and testing modern
integrated circuits, automatic-test-equipment (ATE) archi-
Manuscript received June 15, 2004; revised September 13, 2005. This work
was supported by LTX Corporation, Westwood, MA, and by the International
Test Conference Endowment at Northeastern University.
L. Schiano, M. Momenzadeh, F. Zhang, Y. J. Lee, Y.-B. Kim, and
F. Lombardi are with the Electrical and Computer Engineering Department,
Northeastern University, Boston, MA 02115 USA (e-mail: lschiano@ece.
neu.edu; firstname.lastname@example.org; email@example.com; firstname.lastname@example.org;
T. Kane, S. Max, and P. Perkins are with LTX Corporation, Westwood, MA
02090 USA (e-mail: email@example.com; firstname.lastname@example.org).
F. J. Meyer is with the Electrical and Computer Engineering Department,
Wichita State University, Wichita, KS 67260 USA (e-mail: fred.meyer@
Digital Object Identifier 10.1109/TIM.2006.861531
decades, so-called per-pin architectures have been developed 39
to provide flexibility in allocating to each channel its own TG. 40
In this type of architecture, all components (except for the test 41
processor) are integrated on a single board. Recently, ATEs 42
have been designed based on a per-pin test-processor architec- 43
ture, in which nearly all system components are integrated onto 44
a single chip.
This evolution has provided excellent test flexibility and 46
compactness, and has lowered per-chip costs. However, the new 47
generation of ATEs must provide high-frequency functionality 48
for testing high-performance devices-under-test (DUTs) with 49
no compromise on timing. Furthermore, the output-signal in- 50
tegrity of these ATE systems has become critical, because the 51
clock speed of the DUT is often in the gigahertz region. As 52
ATEs provide the necessary instrumentation for the generation 53
of tests and signals to the DUT at a high operating frequency, 54
jitter has emerged as a critical parameter . Also, a number 55
of chips may be simultaneously tested on an ATE, and testing 56
involves many pins on the same chip, so skew must be within 57
tolerable limits among signals (for different pins of the same 58
DUT) and DUTs (in the same or different boards). In multisite 59
testing, for example, the quality and repeatability of timing 60
require a very low jitter for reliable test results. To guarantee 61
quality, an evaluation of the timing jitter must be performed. 62
If the jitter is excessive, then corrective steps must be taken to 63
Among many signal-integrity problems, jitter due to radi- 65
ated electromagnetic interference (EMI) from switching power 66
supplies has raised concerns that are addressed in this paper. 67
The goal of this paper is to provide, through experimental 68
modeling, the framework by which jitter due to radiated EMI 69
can be predicted. A measurement methodology and a quali- 70
tative analysis (based on experimental results) are described. 71
While in , a time-domain-based technique was proposed 72
to measure the timing jitter. In this paper, frequency-domain- 73
based measurements are employed.
0018-9456/$20.00 © 2006 IEEE
supply module, a chiller system, a reference clock generator,
and multiple test-head boards, such as the one whose block
diagram is shown in Fig. 1.
A test-head board consists of memories, test-pattern gen-
erators, TGs, pin electronics, and programmable parametric-
measurement-function units. The memories store the test
vectors and the measured data collected from the DUT. The pat-
tern and TGs provide patterns and timing signals, respectively.
The pin-electronics circuitry merges the timing, pattern, and
format information to drive the DUT pin and compare the DUT
outputs with the expected data. The programmable parametric-
measurement unit acquires the dc-output parameters from the
The test-head board is made of circuits which require several
supply-voltage levels. DC–DC converters are usually utilized to
generate supply voltages. The use of dc–dc-converter technol-
ogy has several advantages .
compensating for a fault).
2IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Fig. 1. Block diagram of a test-head board in an ATE.
II. SIGNAL-INTEGRITY PROBLEM AND
This section introduces jitter problems due to radiated EMI
noise in the test-head board of an ATE and outlines a model for
the proposed analysis.
A. Test-Head Board and Signal-Integrity Problem
The ATE system under consideration consists of a power-
1) Converters are small enough to be mounted on the test- 107
head printed circuit board (PCB).
2) Converters can generate virtually any desired voltage 109
level, independent of the input level.
3) They are usually cheaper, smaller, and much more effi- 111
cient than linear power-supply modules.
However, dc–dc converters may cause EMI in the test- 113
head board due to switching and large current transients . 114
Therefore, the jitter of the test signal may be increased. At 115
current ATE operating frequencies, the timing margin of a 116
test measurement has significantly narrowed; moreover, it may 117
become worse due to the increasing clock speed by which 118
the ATE must operate for testing the DUT. The presence of 119
timing jitter can thus have a catastrophic impact on the test 120
outcome, as a good DUT could be diagnosed as faulty (due to 121
the jitter invalidating the timing measurement), or a bad device 122
may be accepted (if the jitter moves the timing in a direction 123
B. Phase-Noise Model
signal from its desired (ideal) position. An extensive treatment 127
of jitter can be found in  and .
In this paper, the phase-noise model has been adopted to 129
characterize the jitter . For the jitter in an ATE, this model 130
allows one to estimate the time-domain properties from the 131
From (3), as vn(t) = θ(t)Acsin(ωct), and the analysis
of , then
SCHIANO et al.: MEASURING THE TIMING JITTER OF ATE IN THE FREQUENCY DOMAIN3
noise-spectrum measurements using a spectrum analyzer. This
method is very convenient for high-frequency signals because
it eliminates the slow and difficult process of measuring jitter
in the time domain. In this section, the phase-noise model
is derived for a sinusoidal clock. The analysis of only the
fundamental component of a square-wave signal (as the test-
head-board target signal) is adequate for measuring a jitter of
small value . The clock frequency that is used as reference,
the jittering signal is modeled by the phase-modulated signal as
x(t) = Accos[ωct + θ(t)]
where Acand ωcare the amplitude and angular frequency of the
carrier (i.e., the fundamental component of the target signal),
respectively. From (1), the phase noise can be expressed as
timing jitter by
Furthermore, for a small phase noise, (1) can be approxi-
x(t) = Accosωct − θ(t)Acsin(ωct) = vs(t) + vn(t)
where vs(t) and vn(t) are the signal and noise components of
the jittering signal, respectively. Equation (3) shows that in the
frequency domain, the jitter can be observed as sidebands of the
θ(t) is considered to be a signal given by
θ(t) = Aisin(ωit)
where Ai is the magnitude of the injected signal and ωi is
the frequency of the injected signal. Equation (3) can then be
By considering (2) and (6) (and the analysis of ), then
Equation (7) translates the jitter spectral components (mea-
sured through a spectrum analyzer) to the time domain. From
(5), the frequencies of the spectral components occur at the
carrier frequency minus theinjected frequency and atthecarrier
frequency plus the injected frequency, respectively.
Fig. 2.Circuit diagram of the adapter board .
III. EXPERIMENTAL SETUP AND METHODOLOGY164
In this section, a methodology for measuring jitter is pro- 165
posed. An adapter board was designed to make a high-quality 166
connection to the clock signal to be measured.
A. Experimental Procedure
To measure the jitter generated by the radiated EMI on the 169
test-head board, the following procedure is proposed.
1) H-field emission measurement from the test-head 171
board: The H-field is measured on a fully powered test- 172
head board near the dc–dc converters with a close-field 173
probe and a spectrum analyzer . In addition, H-field 174
emissions are measured at other locations on the board.
2) H-field generation: Using a coil and a function gen- 176
erator, an H-field is injected along the test-signal- 177
generation path, which consists of the phase-locked loop 178
3) Jitter measurement: The jitter is measured while apply- 181
ing various H-fields to the signal path. To ensure that the 182
measured jitter is only due to the forced H-field, the latter 183
is generated at frequencies at which no other spectral 184
component have been previously identified.
4) Analysis:TheratiooftheappliedH-fieldtotheoriginally 186
measured H-field is an indication of the sensitivity of 187
timing in the presence of the dc–dc converters. A plot 188
of the measured jitter versus EMI noise (magnitude and 189
frequency) is then drawn. Qualitative results for the jitter 190
dependence on the H-field-generator orientation (towards 191
the target board) are also presented.
B. Adapter-Board Design
An adapter board  has been employed to access a target 194
signal on the test-head board. For measuring the jitter, issues 195
such as connectivity, ground noise, and impedance matching 196
must be addressed. Consistent results cannot be otherwise 197
guaranteed in the experiments. In general, if timing margins 198
are large, a small jitter component due to connectivity is not 199
critical. However, if the jitter requirement is in the picosecond 200
must be secured. Also, even though ground noise is not strictly
jitter, it can be regarded as such when timing is measured in
its presence. Ground noise is derived from possible unstable
ground connections and impedance mismatching, as related
to connections made in the jitter measurement; ground noise
can randomly change, thus causing measurement results to
be inconsistent. As the test-head board is designed with a
50-Ω impedance matching for the transmission path, additional
connections may impair impedance matching, thus resulting in
an erroneous measurement. This problem occurs when uncon-
trolled or unstable connections are present.
The adapter board used in this paper and in  is com-
patible with the test-head board and allows full compliance
with ATE operation. Its design allows stable connections to
be maintained, reduces ground noise, and does not impair
impedance matching in the transmission path. Its circuit dia-
gram is shown in Fig. 2. This circuit consists of a buffer circuit,
a switching-power-supply module, several capacitors (power 219
and coupling), and termination resistors. The input-signal fre- 220
quency F_IN (Fig. 2) is greater than 1 GHz and the power 221
supply comes from the test-head board. The components are 222
1) C1and C2are ac coupling capacitors; C3through C7are 224
used as power-bypass capacitors for the various power 225
2) Some supply voltages come from the test-head board. 227
The supply power for the buffer circuit is generated 228
4IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Fig. 3.Photograph of the adapter board .
Fig. 4.Experimental setup to measure the dc–dc-converter emission.
MEASURED H-FIELD FROM THE dc–dc CONVERTERS
Fig. 5.Jitter-measurement configuration.
region (as for the considered ATE system), a stable connection
H-FIELDS [w AMPS PER METER] AT DIFFERENT FREQUENCIES
GENERATED BY APPLYING AT THE COIL INPUT A SINUSOIDAL SIGNAL
Fig. 6. Loop filter of the PLL.
external H-Field of 158 dB · µA/m at 500 kHz.
Noise at the input of the PLL filter resulting from the application of an
tified as the main EMI source in the test-head board), the
following equipment has been used: two commercial close-field
probes, a preamplifier, and a spectrum analyzer.
The measurement method employed for the test-head board
is similar to the one described in . Fig. 4 shows the experi-
mental setup. The close-field magnetic probe, which has been
applied close to the dc–dc converters, measures the radiated
H-field that is generated. The probe’s output is connected to a
preamplifier and then to the spectrum analyzer. The gain of the
signal paths (including preamplification and the probe-antenna
factor) is considered for accurate H-field measurements.
In the first experiment, two different probes have been
used; they cover the frequency ranges of 9 kHz to
30 MHz and 30 MHz to 1 GHz, respectively. All frequen-
cies (up to 1 GHz) have been scanned to find the spectral
components of the produced emissions. The measured results
show that the peak of the H-field occurs at around 200 kHz,
of the instants in which the same clock edge crossed that 274
threshold. A fixed number of samples (given by 5000) for 275
the histogram were used in all measurements to obtain con- 276
sistent results. An external trigger (in the frequency range 277
of gigahertz) was provided by the means of a high-precision 278
splitter at the input of the digital oscilloscope . The high 279
frequency of the experiments and the sensitivity of the instru- 280
mentation to environmental noise exacerbated the complexity 281
of the measurements. In particular, results were often affected 282
by spurious trigger jitter components, which suggested that a 283
SCHIANO et al.: MEASURING THE TIMING JITTER OF ATE IN THE FREQUENCY DOMAIN5
Fig. 8.Spectra around the fundamental component of the target signal before and after the application of the external H-field.
from the small switching-power-supply module on the
3) R1,2 are pull-down resistors; R3,4 are back-matching
resistors which, together with the internal 7-Ω resistance
of the buffer, accomplish the 50-Ω impedance matching.
a 50-Ω impedance is 0.110 in .
5) A microminiature coaxial (MMCX) connector is used,
because spacing between the adapter board and the test-
head board is very tight.
A picture of the manufactured adapter board that has been
used to capture the target signal from the test head, is shown
in Fig. 3.
IV. EXPERIMENTAL MEASUREMENTS AND RESULTS242
Experimental measurements and results (obtained by the
procedure introduced in Section III-A) are presented in more
A. On-Board DC–DC-Converter-Emission Measurements
To measure the emission from the dc–dc converters (iden-
MEASURED rms JITTER BY APPLYING H-FIELDS OF DIFFERENT
MAGNITUDE AT DIFFERENT FREQUENCIES
which is the same as the switching frequency of the three 265
given in Table I. Very little energy was observed at frequencies 267
above 1 MHz.
B. Jitter Measurement: Experiment Description
Preliminary experiments were made using a high-frequency 270
digital oscilloscope (in the histogram mode) to observe the 271
jitter. The rms value of the jitter was found by using a 272
fixed voltage-threshold interval and observing the distribution 273