sor, pattern generator, and timing generator (TG)]; in the last
The remaining sections are organized as follows. Section II 75
discusses the basic issues associated with signal integrity re- 76
volving around dc–dc converters. Furthermore, it introduces 77
an analytical model for jitter that is amenable to a frequency- 78
domain-measurement approach. A methodology for measuring 79
the jitter due to radiated EMI is then proposed in Section III, 80
followed by experimental results in Section IV. Finally, con- 81
clusions are drawn in Section V.
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 20061
Measuring the Timing Jitter of ATE
in the Frequency Domain
Luca Schiano, Student Member, IEEE, Mariam Momenzadeh, Student Member, IEEE,
Fengming Zhang, Young Jun Lee, Student Member, IEEE, Thomas Kane, Member, IEEE,
Solomon Max, Life Senior Member, IEEE, Philip Perkins, Member, IEEE,
Yong-Bin Kim, Senior Member, IEEE, Fabrizio Lombardi, Senior Member, IEEE,
and Fred Jackie Meyer, Member, IEEE
Abstract—The objective of this paper is to provide a framework
by which jitter, in the output signals of a test-head board in an
automatic test equipment (ATE), can be measured. In this paper,
jitter phenomena caused by radiated electromagnetic interference
(EMI) noise are considered. EMI noise is mainly present in the test
head of an ATE as result of the activity of the dc–dc converters.
An analysis has been pursued to establish the areas of the
test-head board that are most sensitive to EMI noise. The most
sensitive part of the test-head board has been found to occur
in the loop filter of the phase-locked loop (PLL) that is used
to obtain a high-frequency clock for the timing generator (TG).
Different H-fields are then externally applied to the loop filter to
verify the behavior of the output signal in terms of rms jitter.
A frequency-domain methodology has been employed for the
rms-jitter measurements. The rms-jitter variation for the radiated
EMI magnitude and frequency has been characterized. Also, the
orientation of the external H-field source has been investigated
with respect to the target board and its effects on the measured
rms jitter. For measuring the jitter, an interface circuitry has been
designed on an adapter board to circumvent ground noise and
connectivity problems arising from the test-head environment.
Index Terms—Automatic test equipment, electromagnetic-
interference (EMI)-induced jitter, frequency domain, jitter char-
acterization, jitter measurement, test-head board.
tectures have undergone radical changes in operation and de-
sign . Past ATE architectures were based on shared resources
[i.e., all channels share components such as the test proces-
O MEET the challenge of designing and testing modern
integrated circuits, automatic-test-equipment (ATE) archi-
Manuscript received June 15, 2004; revised September 13, 2005. This work
was supported by LTX Corporation, Westwood, MA, and by the International
Test Conference Endowment at Northeastern University.
L. Schiano, M. Momenzadeh, F. Zhang, Y. J. Lee, Y.-B. Kim, and
F. Lombardi are with the Electrical and Computer Engineering Department,
Northeastern University, Boston, MA 02115 USA (e-mail: lschiano@ece.
neu.edu; email@example.com; firstname.lastname@example.org; email@example.com;
T. Kane, S. Max, and P. Perkins are with LTX Corporation, Westwood, MA
02090 USA (e-mail: firstname.lastname@example.org; email@example.com).
F. J. Meyer is with the Electrical and Computer Engineering Department,
Wichita State University, Wichita, KS 67260 USA (e-mail: fred.meyer@
Digital Object Identifier 10.1109/TIM.2006.861531
decades, so-called per-pin architectures have been developed 39
to provide flexibility in allocating to each channel its own TG. 40
In this type of architecture, all components (except for the test 41
processor) are integrated on a single board. Recently, ATEs 42
have been designed based on a per-pin test-processor architec- 43
ture, in which nearly all system components are integrated onto 44
a single chip.
This evolution has provided excellent test flexibility and 46
compactness, and has lowered per-chip costs. However, the new 47
generation of ATEs must provide high-frequency functionality 48
for testing high-performance devices-under-test (DUTs) with 49
no compromise on timing. Furthermore, the output-signal in- 50
tegrity of these ATE systems has become critical, because the 51
clock speed of the DUT is often in the gigahertz region. As 52
ATEs provide the necessary instrumentation for the generation 53
of tests and signals to the DUT at a high operating frequency, 54
jitter has emerged as a critical parameter . Also, a number 55
of chips may be simultaneously tested on an ATE, and testing 56
involves many pins on the same chip, so skew must be within 57
tolerable limits among signals (for different pins of the same 58
DUT) and DUTs (in the same or different boards). In multisite 59
testing, for example, the quality and repeatability of timing 60
require a very low jitter for reliable test results. To guarantee 61
quality, an evaluation of the timing jitter must be performed. 62
If the jitter is excessive, then corrective steps must be taken to 63
Among many signal-integrity problems, jitter due to radi- 65
ated electromagnetic interference (EMI) from switching power 66
supplies has raised concerns that are addressed in this paper. 67
The goal of this paper is to provide, through experimental 68
modeling, the framework by which jitter due to radiated EMI 69
can be predicted. A measurement methodology and a quali- 70
tative analysis (based on experimental results) are described. 71
While in , a time-domain-based technique was proposed 72
to measure the timing jitter. In this paper, frequency-domain- 73
based measurements are employed.
0018-9456/$20.00 © 2006 IEEE
supply module, a chiller system, a reference clock generator,
and multiple test-head boards, such as the one whose block
diagram is shown in Fig. 1.
A test-head board consists of memories, test-pattern gen-
erators, TGs, pin electronics, and programmable parametric-
measurement-function units. The memories store the test
vectors and the measured data collected from the DUT. The pat-
tern and TGs provide patterns and timing signals, respectively.
The pin-electronics circuitry merges the timing, pattern, and
format information to drive the DUT pin and compare the DUT
outputs with the expected data. The programmable parametric-
measurement unit acquires the dc-output parameters from the
The test-head board is made of circuits which require several
supply-voltage levels. DC–DC converters are usually utilized to
generate supply voltages. The use of dc–dc-converter technol-
ogy has several advantages .
compensating for a fault).
2IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Fig. 1.Block diagram of a test-head board in an ATE.
II. SIGNAL-INTEGRITY PROBLEM AND
This section introduces jitter problems due to radiated EMI
noise in the test-head board of an ATE and outlines a model for
the proposed analysis.
A. Test-Head Board and Signal-Integrity Problem
The ATE system under consideration consists of a power-
1) Converters are small enough to be mounted on the test- 107
head printed circuit board (PCB).
2) Converters can generate virtually any desired voltage 109
level, independent of the input level.
3) They are usually cheaper, smaller, and much more effi- 111
cient than linear power-supply modules.
However, dc–dc converters may cause EMI in the test- 113
head board due to switching and large current transients . 114
Therefore, the jitter of the test signal may be increased. At 115
current ATE operating frequencies, the timing margin of a 116
test measurement has significantly narrowed; moreover, it may 117
become worse due to the increasing clock speed by which 118
the ATE must operate for testing the DUT. The presence of 119
timing jitter can thus have a catastrophic impact on the test 120
outcome, as a good DUT could be diagnosed as faulty (due to 121
the jitter invalidating the timing measurement), or a bad device 122
may be accepted (if the jitter moves the timing in a direction 123
B. Phase-Noise Model
signal from its desired (ideal) position. An extensive treatment 127
of jitter can be found in  and .
In this paper, the phase-noise model has been adopted to 129
characterize the jitter . For the jitter in an ATE, this model 130
allows one to estimate the time-domain properties from the 131
From (3), as vn(t) = θ(t)Acsin(ωct), and the analysis
of , then
SCHIANO et al.: MEASURING THE TIMING JITTER OF ATE IN THE FREQUENCY DOMAIN3
noise-spectrum measurements using a spectrum analyzer. This
method is very convenient for high-frequency signals because
it eliminates the slow and difficult process of measuring jitter
in the time domain. In this section, the phase-noise model
is derived for a sinusoidal clock. The analysis of only the
fundamental component of a square-wave signal (as the test-
head-board target signal) is adequate for measuring a jitter of
small value . The clock frequency that is used as reference,
the jittering signal is modeled by the phase-modulated signal as
x(t) = Accos[ωct + θ(t)]
where Acand ωcare the amplitude and angular frequency of the
carrier (i.e., the fundamental component of the target signal),
respectively. From (1), the phase noise can be expressed as
timing jitter by
Furthermore, for a small phase noise, (1) can be approxi-
x(t) = Accosωct − θ(t)Acsin(ωct) = vs(t) + vn(t)
where vs(t) and vn(t) are the signal and noise components of
the jittering signal, respectively. Equation (3) shows that in the
frequency domain, the jitter can be observed as sidebands of the
θ(t) is considered to be a signal given by
θ(t) = Aisin(ωit)
where Ai is the magnitude of the injected signal and ωi is
the frequency of the injected signal. Equation (3) can then be
By considering (2) and (6) (and the analysis of ), then
Equation (7) translates the jitter spectral components (mea-
sured through a spectrum analyzer) to the time domain. From
(5), the frequencies of the spectral components occur at the
carrier frequency minus theinjected frequency and atthecarrier
frequency plus the injected frequency, respectively.
Fig. 2.Circuit diagram of the adapter board .
III. EXPERIMENTAL SETUP AND METHODOLOGY 164
In this section, a methodology for measuring jitter is pro- 165
posed. An adapter board was designed to make a high-quality 166
connection to the clock signal to be measured.
A. Experimental Procedure
To measure the jitter generated by the radiated EMI on the 169
test-head board, the following procedure is proposed.
1) H-field emission measurement from the test-head 171
board: The H-field is measured on a fully powered test- 172
head board near the dc–dc converters with a close-field 173
probe and a spectrum analyzer . In addition, H-field 174
emissions are measured at other locations on the board.
2) H-field generation: Using a coil and a function gen- 176
erator, an H-field is injected along the test-signal- 177
generation path, which consists of the phase-locked loop 178
3) Jitter measurement: The jitter is measured while apply- 181
ing various H-fields to the signal path. To ensure that the 182
measured jitter is only due to the forced H-field, the latter 183
is generated at frequencies at which no other spectral 184
component have been previously identified.
4) Analysis:TheratiooftheappliedH-fieldtotheoriginally 186
measured H-field is an indication of the sensitivity of 187
timing in the presence of the dc–dc converters. A plot 188
of the measured jitter versus EMI noise (magnitude and 189
frequency) is then drawn. Qualitative results for the jitter 190
dependence on the H-field-generator orientation (towards 191
the target board) are also presented.
B. Adapter-Board Design
An adapter board  has been employed to access a target 194
signal on the test-head board. For measuring the jitter, issues 195
such as connectivity, ground noise, and impedance matching 196
must be addressed. Consistent results cannot be otherwise 197
guaranteed in the experiments. In general, if timing margins 198
are large, a small jitter component due to connectivity is not 199
critical. However, if the jitter requirement is in the picosecond 200
must be secured. Also, even though ground noise is not strictly
jitter, it can be regarded as such when timing is measured in
its presence. Ground noise is derived from possible unstable
ground connections and impedance mismatching, as related
to connections made in the jitter measurement; ground noise
can randomly change, thus causing measurement results to
be inconsistent. As the test-head board is designed with a
50-Ω impedance matching for the transmission path, additional
connections may impair impedance matching, thus resulting in
an erroneous measurement. This problem occurs when uncon-
trolled or unstable connections are present.
The adapter board used in this paper and in  is com-
patible with the test-head board and allows full compliance
with ATE operation. Its design allows stable connections to
be maintained, reduces ground noise, and does not impair
impedance matching in the transmission path. Its circuit dia-
gram is shown in Fig. 2. This circuit consists of a buffer circuit,
a switching-power-supply module, several capacitors (power 219
and coupling), and termination resistors. The input-signal fre- 220
quency F_IN (Fig. 2) is greater than 1 GHz and the power 221
supply comes from the test-head board. The components are 222
1) C1and C2are ac coupling capacitors; C3through C7are 224
used as power-bypass capacitors for the various power 225
2) Some supply voltages come from the test-head board. 227
The supply power for the buffer circuit is generated 228
4IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Fig. 3.Photograph of the adapter board .
Fig. 4. Experimental setup to measure the dc–dc-converter emission.
MEASURED H-FIELD FROM THE dc–dc CONVERTERS
Fig. 5.Jitter-measurement configuration.
region (as for the considered ATE system), a stable connection
H-FIELDS [w AMPS PER METER] AT DIFFERENT FREQUENCIES
GENERATED BY APPLYING AT THE COIL INPUT A SINUSOIDAL SIGNAL
Fig. 6.Loop filter of the PLL.
external H-Field of 158 dB · µA/m at 500 kHz.
Noise at the input of the PLL filter resulting from the application of an
tified as the main EMI source in the test-head board), the
following equipment has been used: two commercial close-field
probes, a preamplifier, and a spectrum analyzer.
The measurement method employed for the test-head board
is similar to the one described in . Fig. 4 shows the experi-
mental setup. The close-field magnetic probe, which has been
applied close to the dc–dc converters, measures the radiated
H-field that is generated. The probe’s output is connected to a
preamplifier and then to the spectrum analyzer. The gain of the
signal paths (including preamplification and the probe-antenna
factor) is considered for accurate H-field measurements.
In the first experiment, two different probes have been
used; they cover the frequency ranges of 9 kHz to
30 MHz and 30 MHz to 1 GHz, respectively. All frequen-
cies (up to 1 GHz) have been scanned to find the spectral
components of the produced emissions. The measured results
show that the peak of the H-field occurs at around 200 kHz,
of the instants in which the same clock edge crossed that 274
threshold. A fixed number of samples (given by 5000) for 275
the histogram were used in all measurements to obtain con- 276
sistent results. An external trigger (in the frequency range 277
of gigahertz) was provided by the means of a high-precision 278
splitter at the input of the digital oscilloscope . The high 279
frequency of the experiments and the sensitivity of the instru- 280
mentation to environmental noise exacerbated the complexity 281
of the measurements. In particular, results were often affected 282
by spurious trigger jitter components, which suggested that a 283
SCHIANO et al.: MEASURING THE TIMING JITTER OF ATE IN THE FREQUENCY DOMAIN5
Fig. 8.Spectra around the fundamental component of the target signal before and after the application of the external H-field.
from the small switching-power-supply module on the
3) R1,2 are pull-down resistors; R3,4 are back-matching
resistors which, together with the internal 7-Ω resistance
of the buffer, accomplish the 50-Ω impedance matching.
a 50-Ω impedance is 0.110 in .
5) A microminiature coaxial (MMCX) connector is used,
because spacing between the adapter board and the test-
head board is very tight.
A picture of the manufactured adapter board that has been
used to capture the target signal from the test head, is shown
in Fig. 3.
IV. EXPERIMENTAL MEASUREMENTS AND RESULTS 242
Experimental measurements and results (obtained by the
procedure introduced in Section III-A) are presented in more
A. On-Board DC–DC-Converter-Emission Measurements
To measure the emission from the dc–dc converters (iden-
MEASURED rms JITTER BY APPLYING H-FIELDS OF DIFFERENT
MAGNITUDE AT DIFFERENT FREQUENCIES
which is the same as the switching frequency of the three 265
given in Table I. Very little energy was observed at frequencies 267
above 1 MHz.
B. Jitter Measurement: Experiment Description
Preliminary experiments were made using a high-frequency 270
digital oscilloscope (in the histogram mode) to observe the 271
jitter. The rms value of the jitter was found by using a 272
fixed voltage-threshold interval and observing the distribution 273
Table II shows the obtained values (as measured by the close-
field probes) with sinusoidal input signals at 250 kHz, 500 kHz,
and 1 MHz, respectively, and amplitude linearly increasing
from 1Vppto 10Vppwith a 1Vppstep. As in Table II, due to
the coil characteristic impedance, higher values of the H-field
and wider ranges were generated at smaller frequencies. How-
ever, the induced jitter was obtained with respect to the EMI
magnitude at each frequency. Unless otherwise mentioned, the
external H-field was intended to be generated with the coil
having its magnetic axis perpendicular to the board plane. A
qualitative analysis of the effects is discussed in a later section
by considering different orientations.
The most sensitive part of the TG’s PLL was identified as the
loop filter, whose schematic diagram is shown in Fig. 6. A high
sensitivity to EMI occurred when the external H-field generator
was applied close to the closed loop A (that consists of R1, R2,
C1, and Cinin Fig. 6).
Fig. 8 shows two spectra plots around the fundamental com- 329
ponent of the target signal. The plot on the left is the spectrum 330
of the gigahertz signal that the PLL generates when no external 331
noise is applied. The fundamental component is about 50 dB 332
above the nearest spurious component. The observed spurious 333
components are related to the dc–dc converters that are used 334
to power the board. The spectrum on the right was generated 335
after applying a 250 kHz external H-field to the PLL loop filter. 336
When the external H-field was applied, a component appeared 337
6 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Fig. 9.Measured rms jitter by applying H-fields of different magnitude at different frequency.
frequency-domain-based phase-noise model would be a more
reliable technique for measurement.
The experimental configuration used for the measurement of
the jitter is shown in Fig. 5. As previously described, a spectrum
analyzer was used to observe the jitter with the mathematical
model introduced in Section II-B. After the experimental con-
figuration was set up, an external H-field was generated and
directed at various points on the board to determine those areas
that were most sensitive. As for the external H-field generator,
a coil has been made by winding a thin wire in a three-
layer structure. The coil was shielded to prevent the E-field
from capacitively coupling into the board. Therefore, only the
H-field contribution to the measured jitter has been considered.
As mentioned previously, the H-fields were generated at dif-
ferent frequency and magnitude, spanning wider ranges than
indicated by previous dc–dc-converter-emission measurements.
MEASURED rms JITTER APPLYING A 173-dB · µA/m H-FIELD AT
As an example, Fig. 7 shows the noise induced by an external 317
H-field of 158 dB · µA/m at 500 kHz for node Vain Fig. 6. The 318
applied noise results in an ac coupling at 500 kHz with a peak- 319
to-peak value (denoted as ∆ in this figure) of 75 mV. A similar 320
type of noise was observed at the input of the voltage-controlled 321
oscillator (VCO). As the reference signal at the VCO was not 322
stable, it causes the phase noise (frequency fluctuations) to be 323
added to the sinusoidal output. Thus, the timing signal from 324
the TG in the test-head board was affected by EMI-induced 325
circuitry, then jitter phenomena occur at the output signal of the 327
a different frequency. The noise was applied to the test-head
board to investigate its effects on the rms jitter of the board
output signal. When applying H-fields with magnitude and
frequency similartothemeasured dc–dc emission,the observed
jitter was acceptable. Large rms-jitter values were obtained
with H-fields of higher magnitudes, as describing the worst
case scenario in the ATE. This allows a board designer to
quantitatively estimate the amount of jitter that is being added
by the dc–dc converters powering adjacent boards in an ATE
The applied H-fields and the corresponding measured rms-
jitter values are shown in Table III and Fig. 9. These values
were obtained by solving (7) with the values observed on the
spectrum analyzer. The plot shows a linear dependence of the
measured jitter with the H-field magnitude. Moreover, the slope
of the curves decreases when the frequency increases, thus
showing a higher sensitivity of jitter phenomena to lower EMI
frequencies. Moreover, experiments have been performed to 379
give a qualitative description of the jitter’s behavior for polar- 380
ization between the externally induced H-field and the target 381
board. While keeping the H-field generator (coil) at the same 382
distance from the board, the angle between its magnetic axis 383
and the board plane was varied. As shown in Fig. 11, different 384
angles were considered by pivoting the coil horizontally and 385
Fig. 12 shows the jitter values obtained by applying a 387
250-kHz H-field with the magnitudes reported in Table III, and 388
SCHIANO et al.: MEASURING THE TIMING JITTER OF ATE IN THE FREQUENCY DOMAIN7
Fig. 10.Measured rms jitter by applying a 173-dB · µA/m H-field at different frequency.
at a 250-kHz distance from the fundamental, as expected from
the phase-noise model of the jitter [(3), Section II-B]. Spurious
signals that are visible in the spectrum (and not corresponding
to any application of external noise) are due to EMI effects from
the on-board circuitry. To clearly identify the applied H-field as
the only cause of a measured spectral component, its frequency
was chosen to occur in a band in which the board’s spurious
signals were minimal so that the amount of jitter caused by
the externally applied H-field could be distinguished from the
spurious signals produced by the preexisting on-board circuitry.
In all experiments, the frequencies were chosen with the current
features and the expected trend in test-head-board design.
C. Jitter-Measurements Results
Starting from the values observed for the dc–dc converter
emission, H-fields of increasing magnitude were generated at
Relative movements of the H-field generator with respect to the
noise frequencies. This behavior appears valid for frequencies 370
up to 1 MHz. For higher frequencies of EMI noise (not consid- 371
ered in this paper), the amount of jitter also increased.
Furthermore, Table IV and Fig. 10 show the results obtained 373
for a fixed H-field magnitude of 173 dB · µA/m. By increasing 374
the frequency, a polynomial curve whose fitting equation is 375
included in Fig. 10 was obtained (R2in Fig. 10 indicates the de- 376
gree of accuracy of the proposed fitting method). The frequency 377
dependence is related to the loop filter, which attenuates higher 378
8 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
and the board plane with a vertical movement.
Jitter measurements obtained by applying H-fields of increasing magnitude and fixed frequency (250 kHz) and varying the angle between the coil axis
and the board plane with a horizontal movement.
Jitter measurements obtained by applying H-fields of increasing magnitude and fixed frequency (250 kHz) and varying the angle between the coil axis
varying (Fig. 11) the angle “vertically” between the coil polar
axis and the board. As expected, the results show that the jitter
is linear with respect to the H-field magnitude, and there are
sensitivities at different angles, thus highlighting the coupling
effects. In particular, the highest sensitivity occurs at an angle
of 90◦between the coil axis and the board plane. Fig. 13
shows the results obtained by pivoting the coil horizontally
and applying H-fields of different magnitude (Table III) for
a frequency of 250 kHz. As for the vertical case, the jitter 397
is linear with respect to the H-field magnitude with slopes 398
corresponding to different angles. Again, the highest sensitivity 399
corresponds to an angle of 90◦between the coil axes and the 400
board plane. Analogous experiments have been performed for 401
frequencies up to 1 MHz. The behavior is the same as the 402
ones shown in Figs. 12 and 13. The measured jitter is however 403
less than the one observed by applying a 250-kHz H-field, 404
and was involved in microcontroller design, liquid- 516
crystal-display (LCD) controller design, and sound 517
IC design. Currently, he is working for Nextchip Co., 518
Ltd., Korea. His research interests include high-speed low-power very-large- 519
scale-integration (VLSI) circuit design and analog VLSI circuit design.
SCHIANO et al.: MEASURING THE TIMING JITTER OF ATE IN THE FREQUENCY DOMAIN9
thus confirming the higher sensitivity of the loop to a lower
As new generations of test-head boards are performing most
measurement functions (that in traditional ATEs were per-
formed in the mainframe), a higher accuracy must be achieved
for high-speed DUTs. However, to assemble circuits with dif-
ferent supply-voltage levels, it is common to include dc–dc
converters in the head card. The presence of nearby switching
power supplies can potentially introduce jitter, so jitter must
be carefully controlled. A jitter-measurement methodology has
been proposed; by analyzing the experimental results, it has
been shown that a relationship exists for the jitter variation
with respect to EMI emission. To characterize the radiated
generator has been designed. Experiments have been conducted
in which H-fields of different magnitude and frequency were
injected into the board. The corresponding jitter variations have
The jitter was measured at the output of the test-head
board using an adapter board, to circumvent ground noise and
connectivity problems  arising from the head environment.
Using the phase-noise model  as basis, measurements have
been made in a frequency domain; subsequently, the obtained
results have been converted to a time domain. When the H-field
strength is applied and varied at the loop filter of the PLL (that
was previously identified as the most sensitive area of the head
board), a jitter variation was observed. A direct relationship
with the applied H-field has been established for the rms jitter
with respect to the H-field magnitude and frequency. The mea-
surement of the field allows the physical design to be verified
for the rms jitter caused by the radiated EMI. It is anticipated
that these techniques and the framework provided by this paper
will be utilized to design test-head boards in ATEs that operate
at very high frequencies.
 M. Goto and K. Hilliges, “The DFT age ATE architecture—The multi-port
ATE,” in Proc. Semicon, Semi Tech. Symp., Chiba, Japan, 2000, vol. 5,
 M. Keating, “Fundamental limits to timing accuracy,” in Proc. IEEE Int.
Test Conf. (ITC), Washington, DC, 1986, pp. 756–762.
 Y. J. Lee, T. Kane, J.-J. Lim, L. Schiano, Y.-B. Kim, F. J. Meyer,
F. Lombardi, and S. Max, “Analysis and measurement of timing jitter
induced by radiated EMI noise in ATE,” IEEE Trans. Instrum. Meas.,
vol. 52, no. 6, pp. 1749–1755, Dec. 2003.
 J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power
Electronics. Reading, MA: Addison-Wesley, Jun. 1992.
 M. Mardiguian, Controlling Radiated Emissions by Design, 2nd ed.
Boston, MA: Academic, 2001.
 T. J. Yamaguchi, M. Ishida, M. Soma, D. Halter, R. Raina, and J. Nissen,
“A method for measuring the cycle-to-cycle period jitter of high-frequency
clock signals,” in Proc. 19th IEEE Very Large Scale Integration (VLSI) Test
Symp., Marina Del Rey, CA, May 2001, pp. 102–110.
 M. Shimanouchi, “An approach to consistent jitter modeling for various
jitter aspects and measurement methods,” in Proc. IEEE Int. Test Conf.
(ITC), Baltimore, MD, 2001, pp. 848–857.
 R. Thottappillil, V. Scuka, J. Eriksson, A. Eriksson, and P. Ohman, “Es-
timation of fields radiated by a PCB from close magnetic field mea-
surements,” in Proc. Int. Conf. Electromagnetic Compatibility, Coventry,
U.K., 1997, pp. 89–93.
 Designing with LVDS. Application Note 905. [Online]. Available: http://
Luca Schiano (S’XX) was born in Napoli, Italy, in 467
1975. He received the “Laurea” degree in electronic 468
engineering from University of Bologna, Bologna, 469
Italy, in 2001. He is currently working towards the 470
Ph.D. degree in computer engineering at the Electri- 471
cal and Computer Engineering Department, North- 472
eastern University, Boston, MA.
He is interested in research on IC testing, 474
automatic test equipment (ATE), on-line testing, 475
reliability, and nanotechnologies.
Mariam Momenzadeh (S’XX) was born in Tehran, 477
Iran. She received the B.Sc. degree in electrical 478
engineering from Sharif University of Technology, 479
Tehran, in 1999, and the M.Sc. degree in computer 480
engineering and science from University of Con- 481
necticut, Storrs, in 2003. She is currently working 482
towards the Ph.D. degree at the Electrical and Com- 483
puter Engineering Department, Northeastern Univer- 484
sity, Boston, MA.
She has research interests in testing, design for 486
testability, fault-tolerance issues in digital systems, 487
automatic-test-equipment (ATE) systems, and nanotechnologies.
Province, China, in 1972. He received both the 490
B.S. and the M.S. degrees in industry control and 491
automation from Beijing University of Chemical 492
Technology, Beijing, China, in 1994 and 1997, 493
respectively. In April 2005, he received the Ph.D. 494
degree in electrical engineering from Northeastern 495
University, Boston, MA, where he worked on elec- 496
tromagnetic-interference (EMI) noise on clock-jitter 497
generations, analog IC design for an underwater 498
biomimic robot, and emerging-technology research, 499
mainly on the modeling of signal-electron tunneling transistors and single- 500
electron transistor (SET)-based circuit designs.
From 1997 to 1999, he was with Beijing Hollysys Co., Ltd., as an 502
honored Design Engineer involved in microprocessor-based hardware and 503
software designs for I/O stations of distributed computer control systems. 504
Since August 2004, he has been working at the Digital Division of LTX 505
Corporation, San Jose, CA, as a Hardware Design Engineer on automatic- 506
test-equipment (ATE) product designs.
was borninHeilongjiang 489
Young Jun Lee (S’XX) was born in Seoul, Republic 508
of Korea, in 1968. He received the B.S. and M.S. 509
sity, Seoul, in 1992 and 1994, respectively, and the 511
Ph.D. degree from Northeastern University, Boston,
MA, in 2004.
From 1994 to 2000, he worked for Samsung 514
Electronics, Korea, as a Senior Design Engineer, 515
Thomas Kane (M’XX) received the B.S.E.E. and M.S.Phys. degrees from the 521
University of Connecticut, Storrs, in 1994 and 1996, respectively.
He was with Thermawave, Fremont, CA, as a Field Applications Engineer 523
involved in thin-film metrology equipment from 1997 to 2000. He is now with 524
LTX Corporation, Westwood, MA, as a Systems Analog Engineer.
From 1996 to 1998, he was with Sun Microsystems, Palo Alto, CA, as an
Individual Contributor and was involved in 1.5-GHz Ultra Sparc5 CPU chip
design. From 1998 to 2000, he was an Assistant Professor in the Department
of Electrical Engineering, University of Utah, Salt Lake City. He is currently
a Zraket Endowed Professor in the Department of Electrical and Computer
Engineering, Northeastern University, Boston, MA. His research focuses on
high-speed low-power very-large-scale-integration (VLSI) circuit design and
10 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 1, FEBRUARY 2006
Solomon Max (S’55–M’58–LM’97–LS’02) re-
ceived the B.S. degree in electrical engineering from
the City College of New York, NY, and the S.M.
and E.E. degrees from the Massachusetts Institute of
He is one of the Founders of LTX Corporation,
Westwood, MA, where he is a Staff Scientist and
LTX Fellow. He is the architect of many calibration
algorithms in LTX systems, and he designed many
instruments in LTX systems. He holds two patents,
one for an analog-to-digital converter and another for
an instrumentation amplifier. He is the author of seven International Test Con-
ference (ITC) papers and three Instrumentation and Measurement Technology
Conference (IMTC) papers.
Mr. Max is a member of the IEEE TC-10 Standards Committee on ana-
log/digital converter (ADC) and Digital/Analog Converter (DAC) Testing and
a member of Tau Beta Pi, Sigma Xi, and Eta Kappa Nu.
Philip Perkins (M’XX) received the S.B., S.M., and
E.E. degrees in electrical engineering from Massa-
chusetts Institute of Technology, Cambridge.
He was previously with Teradyne, Inc., Boston,
MA. He is a Cofounder of LTX Corporation, West-
wood, MA, where he is an LTX Fellow and Staff
Scientist. He has designed instruments for semi-
conductor automatic test equipment (ATE), includ-
ing V/I sources, test heads, and DSP-measuring
instruments. He holds a patent for “mixed signal
device under test board interface.”
Yong-Bin Kim (S’88–M’88–SM’00) was born in
Seoul, South Korea, in 1960. He received the B.S.
degreein electrical engineering fromSogangUniver-
sity, Seoul, in 1982, the M.S. and Ph.D. degrees, both
in computer engineering, from New Jersey Institute
of Technology, Newark, and Colorado State Univer-
sity, Forth Collins, in 1989 and 1996, respectively.
From 1982 to 1987, he was with Electronics and
Telecommunications Research Institute, Seoul, as a
member of Technical Staff. From 1990 to 1993,
he was with Intel Corporation as a Senior Design
Engineer and was involved in microcontroller chip design and Intel P6
microprocessor chip design. From 1993 to 1996, he was with Hewlett-Packard
Co., Fort Collins, as a member of Technical Staff and was involved in HP PA-
8000 Reduced Instruction Set Computer (RISC) microprocessor chip design.
Fabrizio Lombardi (M’82–SM’02) graduated in 577
1977 from the University of Essex, U.K., with the 578
B.Sc. (Hons.) degree in electronic engineering. He 579
received the Master in microwaves and modern op- 580
tics (1978), the Diploma in microwave engineering 581
(1978), and the Ph.D. degree from the University of 582
London, London, U.K. (1982).
He joined the Microwave Research Unit, Univer- 584
sity College London, in 1977. He was previously 585
a Faculty Member at Texas Tech University, Lub- 586
bock, the University of Colorado, Boulder, and Texas 587
Test Conference (ITC) Endowed Professorship at Northeastern University, 589
Boston, MA. At the same institution, during the period 1998–2004, he served as 590
Chair of the Department of Electrical and Computer Engineering. His research 591
interests are testing and design of digital systems, quantumand nanocomputing, 592
automatic-test-equipment (ATE) systems, configurable/network computing, de- 593
fect tolerance, and computer-aided design (CAD) very-large-scale integration 594
(VLSI). He has extensively published in these areas and has edited six books.
Dr. Lombardi has received many professional awards: the Visiting Fel- 596
lowship at the British Columbia Advanced System Institute, University of 597
Victoria, Canada (1988), the Texas Experimental Engineering Station Re- 598
search Fellowship (1991–1992 and 1997–1998), the Halliburton Professorship 599
(1995), the Outstanding Engineering Research Award at Northeastern Uni- 600
versity (2004), and an International Research Award from the Ministry of 601
Science and Education of Japan (1993–1999). He was the recipient of the 602
1985/86 Research Initiation Award from the IEEE/Engineering Foundation and 603
a Silver Quill Award from Motorola–Austin (1996). He was an Associate Editor 604
(1996–2000) of IEEE TRANSACTIONS ON COMPUTERS and a Distinguished 605
Visitor of the IEEE-Computer Society (CS) (1990–1993). Since 2000, he has 606
been the Associate Editor-In-Chief of IEEE TRANSACTIONS ON COMPUTERS. 607
Currently, he is also an Associate Editor of the IEEE Design and Test Magazine 608
and a Distinguished Visitor of the IEEE-CS; he is also the Chair of the 609
Committee on “Nanotechnology Devices and Systems” of the Test Technology 610
Technical Council of the IEEE. He has also been involved in organizing 611
many international symposia, conferences, and workshops sponsored by pro- 612
fessional organizations, as well as Guest Editor of special issues in archival 613
journals and magazines such as the IEEE TRANSACTIONS ON COMPUTERS, 614
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, the 615
IEEE Micro Magazine, and the IEEE Design and Test Magazine. He is the 616
Founding General Chair of the IEEE Symposium on Network Computing and 617
Fred Jackie Meyer (S’85–M’87) received the B.Sc. 619
degree in computer systems engineering from the 620
University of Massachusetts, in 1984, and the Ph.D. 621
degree from the Electrical and Computer Engineer- 622
ing Department, University of Massachusetts, in 623
He was previously at Northeastern University and 625
at Texas A&M University, College Station. He is 626
currently an Assistant Professor of Electrical and 627
Computer Engineering at Wichita State University, 628
Wichita, KS. His research interests include yield 629
modeling and assessment, nanocomputing, and digital design and test. He was 630
Guest Coeditor for the Journal of Electronic Testing: Theory and Applications. 631
Dr. Meyer served as Program Cochair for the 2002 IEEE International Sym- 632
posium on Defect and Fault Tolerance in Very Large Scale Integration (VLSI) 633
Systems (DFT) and General Cochair for DFT 2003. He was an Associate Editor 634
of the IEEE TRANSACTIONS ON COMPUTERS and a Guest Coeditor for IEEE 635
Design and Test 0f Computers.
AUTHOR PLEASE ANSWER ALL QUERIES
AQ1 = Please provide additional information in Ref. .
AQ2 = Please indicate the major field of study.
AQ3 = Please specify when the degree was earned.
AQ4 = Please specify when the degree was earned.
AQ5 = Please specify when the degree was earned.
Notes: 1) Please provide photo for author T. Kane.
2) Please provide IEEE membership history for authors L. Schiano, M. Momenzadeh, Y. L. Lee,
T. Kane, and P. Perkins.
END OF ALL QUERIES