Article

Structural optimization of SUTBDG devices for low-power applications

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
IEEE Transactions on Electron Devices (Impact Factor: 2.06). 04/2005; DOI: 10.1109/TED.2005.843869
Source: IEEE Xplore

ABSTRACT In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-κ gate dielectrics raise the off-state current (IOFF) due to the fringing field-induced barrier lowering effect. Suppressing the IOFF increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed IOFF, devices with less abrupt S/D-channel junctions suffer a drive current (ION) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in ION. The ION of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.

0 Bookmarks
 · 
59 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Leakage power, due to the tunneling gate current, increases aggressively with the scaling of the insulator thickness. Low Standby Power (LSTP) devices are typically designed for low power applications that put strict limits on the gate current. In this work a widely used model for the tunneling gate current in bulk MOSFET is modified to suits the Double-gate (DG) MOSFET. The modification is made to include quantum mechanical effects. Then, the model is used to study the gate leakage in a 16 nm gate length DG MOSFET LSTP transistor that is projected by the International Technology Roadmap for Semiconductors (ITRS) to be fabricated in the year 2015. In this study, the gate current is calculated for different candidates of dielectric materials. Specifically, nine dielectric materials were used. The simulated gate current is found to be 5.36x10 3 A/cm 2 when SiO 2 was used as a dielectric and 338.76 A/cm 2 when Si 3 N 4 was used. These two values exceed the maximum allowed gate current density (J g,limit) projected by ITRS for this device which is 0.188 A/cm 2 . The lowest obtained gate current density was 2.66x10 -11 A/cm 2 when La 2 O 3 and is used.
    National Radio Science Conference, 2009.; 03/2009
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: Rapid device scaling pushes the dimensions of the field effect transistors to the nanometer regime where quantum effects play an important role in determining the transistor characteristics. The Non-equilibrium Green’s function formalism (NEGF) provides a rigorous description of quantum transport in nanoscale devices. The Real-Space (RS) representation is the most accurate yet complex representation used in the NEGF. The geometry of fully-depleted double gate (DG) MOSFETs permits the use of a simpler quasi two-dimensional (2D) representation, the mode-space (MS) which is computationally efficient. This thesis addresses the simulation and design of the nanoscale DG MOSFETs using the NEGF framework in both the RS and MS representations. Different transport models in RS will be implemented in the FETMOSS simulator, whose original version was capable of simulating NEGF using the MS only. In this work, the 2D NEGF simulation methodology and results of DG MOSFETs using the RS approach are presented. A new computationally efficient method for the NEGF in RS is proposed and implemented in the FETMOSS simulator. Other methods existing in the literature were studied, implemented and compared with the proposed one. Moreover, the MS validity is examined by comparison with the RS. Then, a fast method to check the MS validity is investigated and implemented and some ideas are suggested to further reduce the MS computational burden. Exploiting the 2D quantum simulator built in this work, design and simulation of nanoscale DG MOSFET at the end of the International Technology Roadmap for Semiconductors (ITRS) is carried. The design of a 10 nm DG MOSFET is presented using a design optimization procedure. For the first time to be reported, the obtained results show that satisfying both the on-current and the switching speed requirements of the ITRS for the high power device is possible. The use of high-k material gate dielectric for the low standby power 16 nm DG MOSFET is also investigated. Finally, the effect of 2D electrostatics on the nanoscale DG MOSFETs capacitance is studied.
    06/2009, Degree: MSc, Supervisor: Magdy Ibrahim, Hani Fikry and Wael Fikry
  • [Show abstract] [Hide abstract]
    ABSTRACT: Quantum transport simulation in DoubleGate (DG) MOSFETs using the Non-Equilibrium Green's function Formalism (NEGF) in both coupled-mode space (CMS) and real space (RS) is reported. The transport models were implemented in the same simulator and used to simulate near-and long-term's targets of the ITRS for DG MOSFETs. The CMS presents the advantage of simulation time reduction without significant loss of accuracy, when sufficient number of modes is used. The computational burden is reduced by a factor of 7 comparing with RS and the percentage error in the terminal current is less than 0.2 % for the year 2017 target device of the ITRS.
    Engineering and Technology (ICET), 2012 International Conference on; 01/2012