In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-κ gate dielectrics raise the off-state current (IOFF) due to the fringing field-induced barrier lowering effect. Suppressing the IOFF increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed IOFF, devices with less abrupt S/D-channel junctions suffer a drive current (ION) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in ION. The ION of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.
"onventional CMOS technology is predicted to come to its end at the 22 nm node due to the scaling challenges . Advanced devices such as ultra-thin body fully depleted SOI MOSFETs and Double-Gate (DG) MOSFETs are expected to replace the CMOS technology with the latter one found to be the most promising due to better short-channel behavior, lower leakage current, higher drive current, and smaller subthreshold swing . "
[Show abstract][Hide abstract] ABSTRACT: Quantum transport simulation in DoubleGate (DG) MOSFETs using the Non-Equilibrium Green's function Formalism (NEGF) in both coupled-mode space (CMS) and real space (RS) is reported. The transport models were implemented in the same simulator and used to simulate near-and long-term's targets of the ITRS for DG MOSFETs. The CMS presents the advantage of simulation time reduction without significant loss of accuracy, when sufficient number of modes is used. The computational burden is reduced by a factor of 7 comparing with RS and the percentage error in the terminal current is less than 0.2 % for the year 2017 target device of the ITRS.
Engineering and Technology (ICET), 2012 International Conference on; 01/2012
"The non-equilibrium Green's function formalism (NEGF) provides a rigorous description of quantum transport in nanoscale devices . Device simulation based on NEGF is carried out using the so called self-consistent solution method shown in figure 2. The method is composed of two main blocks, Poisson's equation solver and the quantum transport solver. "
[Show abstract][Hide abstract] ABSTRACT: The International Technology Roadmap for Semiconductors (ITRS) projected value for the High Performance (HP) MOSFET channel length is 10 nm at the year 2016. The FinFET is expected to replace the conventional bulk MOSFET beyond the 22 nm node due to the latter's scaling challenges. In this article the design optimization of a 10 nm FinFET is considered. It is shown that the ITRS requirements for the FinFET's driving current and switching speed can be satisfied simultaneously. The on-current and switching speed can be as large as 6734 muA/mum and 24.4 THz compared to the 4590 muA/mum and 5.6 THz of the ITRS projections. It is also shown that the use of a mid-gap work function can satisfy the ITRS requirements. Moreover, factors for better manufacturability like relaxed extension lateral abruptness and increased fin thickness are also considered in the design.
Design & Technology of Integrated Systems in Nanoscal Era, 2009. DTIS '09. 4th International Conference on; 05/2009
"At the same time, it has some disadvantages such as kink and self heating effects . Double-Gate (DG) MOSFETs are attractive candidates to continue the scaling down to gate lengths in the 50 nm to 10 nm range , . ITRS promotes ultra-thin DG MOSFETs as the ideal device structure for ultimate scaling . "
[Show abstract][Hide abstract] ABSTRACT: Leakage power, due to the tunneling gate current, increases aggressively with the scaling of the insulator thickness. Low Standby Power (LSTP) devices are typically designed for low power applications that put strict limits on the gate current. In this work a widely used model for the tunneling gate current in bulk MOSFET is modified to suits the Double-gate (DG) MOSFET. The modification is made to include quantum mechanical effects. Then, the model is used to study the gate leakage in a 16 nm gate length DG MOSFET LSTP transistor that is projected by the International Technology Roadmap for Semiconductors (ITRS) to be fabricated in the year 2015. In this study, the gate current is calculated for different candidates of dielectric materials. Specifically, nine dielectric materials were used. The simulated gate current is found to be 5.36x10 3 A/cm 2 when SiO 2 was used as a dielectric and 338.76 A/cm 2 when Si 3 N 4 was used. These two values exceed the maximum allowed gate current density (J g,limit) projected by ITRS for this device which is 0.188 A/cm 2 . The lowest obtained gate current density was 2.66x10 -11 A/cm 2 when La 2 O 3 and is used.
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