A Direct Power Injection Model for Immunity Prediction in Integrated Circuits

Abstract

This paper introduces a complete simulation model of a direct power injection (DPI) setup, used to measure the immunity of integrated circuits to conducted continuous-wave interference. This model encompasses the whole measurement setup itself as well as the integrated circuit under test and its environment (printed circuit board, power supply). Furthermore, power losses are theoretically computed, and the most significant ones are included in the model. Therefore, the injected power level causing a malfunction of an integrated circuit, according to a given criterion, can be identified and predicted at any frequency up to 1 GHz. In addition to that, the relationship between immunity and impedance is illustrated. Simulation results obtained from the model are compared with measurement results, and these demonstrate the validity of this approach.

Full text

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SUBMITTED TO IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY1
A Direct Power Injection Model for Immunity
Prediction in Integrated Circuits
Ali Alaeldine, Student Member, IEEE, Richard Perdriau, Member, IEEE, Mohamed Ramdani, Member, IEEE, and
Jean-Luc Levant
Abstract—This paper introduces a complete simulation model
of a Direct Power Injection (DPI) setup, used to measure the
immunity of integrated circuits to conducted continuous-wave
interference. This model encompasses the whole measurement
setup itself as well as the integrated circuit under test and its
environment (printed circuit board, power supply). Furthermore,
power losses are theoretically computed, and the most significant
ones are included in the model. Therefore, the injected power
level causing a malfunction of an integrated circuit, according
to a given criterion, can be identified and predicted at any
frequency up to 1 GHz. In addition to that, the relationship
between immunity and impedance is illustrated. Simulation
results obtained from the model are compared to measurement
results and demonstrate the validity of this approach.
Index Terms—EMC, IC, DPI, immunity, modeling, simulation
I. INTRODUCTION
N
tromagnetic disturbances, to which an increasing number of
integrated circuits (IC) are becoming more and more sus-
ceptible. Indeed, the decrease in geometry length induces a
reduction in power supply voltage and, consequently, noise
margin. In order to characterize the behavior of these ICs
to electromagnetic interference, several measurement meth-
ods are currently under standardization process, under the
supervision of the International Electrotechnical Commission
(IEC), one of which is Direct Power Injection (DPI) [1].
However, these methods rely only on measurements, and thus
can not be used for immunity prediction. Therefore, this article
introduces a complete electrical model of a DPI setup, making
it possible to predict the immunity of an IC (i.e. its ability to
withstand electromagnetic interference without exhibiting any
malfunction) on a given printed circuit board (PCB) within the
design phase.
An example of DPI setup is displayed in Fig. 1. Continuous
sine-wave RF power (from 10 MHz to 1 GHz) delivered by
a generator is fed into an amplifier and then injected into a
pin of the IC under test (either a power pin or a signal input
Owadays, the steep growth of mass-market electronic
communication systems is the source of numerous elec-
Ali Alaeldine is with ESEO - 4, rue Merlet-de-la-Boulaye - BP 30926
- 49009 Angers Cedex 01 - France, and with IETR - INSA de Rennes -
20, avenue des Buttes de Coësmes - 35043 Rennes Cedex - France (e-mail:
ali.alaeldine@eseo.fr).
Richard Perdriau and Mohamed Ramdani are with ESEO - 4, rue Merlet-
de-la-Boulaye - BP 30926 - 49009 Angers Cedex 01 - France (e-mail:
richard.perdriau@eseo.fr, mohamed.ramdani@eseo.fr).
Jean-Luc Levant is with ATMEL Nantes - La Chantrerie - Route de Gachet
- 44300 Nantes - France (e-mail: jean-luc.levant@nto.atmel.com).
pin) through a capacitor blocking the DC voltage coming from
the power supply (hence the name of the test). A directional
coupler allows the measurement of incident and reflected
powers by the means of two power meters. The IC under test
works under normal operating conditions; since the one used
in this study is a digital synchronous circuit, it is fed by a
clock signal and a data signal, as explained in Sect. IV-D.3.
First of all, a preliminary study of the power transmitted is
introduced in Sect. II. Then, Sect. III points out the need for
estimating and modeling of power losses in DPI experiments.
The electrical model of the DPI setup itself is presented in
Sect. IV, each part of the system being analyzed separately.
Sect. V deals with the immunity criterion and the simulation
algorithm chosen for this study. Finally, simulation results as
well as comparisons between measurements and simulations
are given in Sect. VI and demonstrate how this electrical model
allows the prediction of the immunity of an IC during a DPI
experiment.
II. THEORETICAL STUDY OF TRANSMITTED POWER
The purpose of the DPI experiment is the characterization
of the immunity of an integrated circuit as a function of the
effective power transmitted to the circuit. However, due to
impedance mismatch, most of the RF power delivered by the
generator is reflected towards the source, and only a small
amount enters the PCB and IC under test. Consequently, the
computation of this effective transmitted power is necessary. It
relies on the knowledge of the impedance ZDUT of the whole
circuit under test, which is extracted from the S11parameter
of the circuit obtained from a vector network analyzer (VNA):
ZDUT = Z01 − S11
1 + S11
(1)
in which Z0 = 50 Ω is the nominal impedance of the
analyzer. Then, the incident power can be computed from this
impedance and the incident voltage VInc:
PInc= IZ0VInc=
VInc2
Re(ZDUT)
(2)
The transmitted power PTranscan then be expressed from the
incident power:
PTrans= (1 − |S11|2) PInc
(3)
0000–0000/00$00.00 c ?2006 IEEE

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SUBMITTED TO IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY2
Fig. 1.
DPI injection system
By replacing the reflection factor by its expression, Eq. 4 is
obtained:
?
ZDUT+ Z0
By separating the real and imaginary parts of ZDUT, the exact
expression of transmitted power can be obtained:
PTrans=1 −
????
ZDUT− Z0
????
2?
PInc
(4)
PTrans=4 Z0Re(ZDUT)
|ZDUT+ Z0|2
PInc
(5)
The expression in Eq. 5 is well suited to the calculation
of PTrans from measurements, owing to the use of power
meters in DPI experiments. However, it is unusable for DPI
electrical modeling and simulation, since power generators
are not available in common circuit simulators. A convenient
solution consists in using a RF voltage source, and expressing
the transmitted power as a function of source voltage instead
of injected power. This can be achieved by combining Eq. 2
and Eq. 5:
PTrans=
4 Z0
|ZDUT+ Z0|2VInc2
(6)
These expressions will be used in Sect. VI-A in order to build
up immunity plots (in dBm) from electrical simulation results
(in V).
III. POWER LOSSES IN DIRECT POWER INJECTION
A. Theoretical estimation of power losses by the Q-factor
method
During a DPI experiment, considerable RF power may
be injected into the populated PCB. However, only a small
amount of this power actually enters the IC under test, the
remainder being either dissipated in other discrete components
or lost. From 10 MHz to 1 GHz, these power losses are due
to many different phenomena: conductive losses, dielectric
losses, radiation, surface waves. A convenient approach to
estimate the relative contributions of these losses is the use
of the quality factor [2].
1) Conductive losses: An approximated formula for the
quality factor due to conductive losses in a PCB track is given
in [3]:
Qc≈h
δs
≈ h
?π µ0µr
ρ
?
f
(7)
in which h is the thickness of the cavity represented by the
whole PCB, and δsis the skin depth. ρ = 1.72 · 10−8Ω · m
is the resistivity of copper, µ0
permeability of vacuum and µr = 1 the relative permeability
of copper. As expected, Qcis proportional to the square root
of f, the injection frequency. Its values are shown for different
frequencies in table I.
2) Dielectric losses: The quality factor of dielectric losses
in a FR4 board is given in [3]:
= 4π · 10−7H · m−1the
Qd=
1
tanδ
(8)
in which tanδ ≈ 0.02 [4] is the loss tangent of the PCB
material. Its value depends on the injection frequency [5], but
remains approximately constant in high frequency for FR4
material.
3) Radiated losses: Radiated losses can be computed from
the cavity model of a PCB [6]. Their quality factor, for the
dominant TM10mode on rectangular PCBs, can be expressed
by:
Qrad≈
3 εrLeλ0
16 p c1Weh≈
3 c Le
16 p c1h We
?µr
εr
1
f
(9)
in which h = 1.6 mm is the thickness of the cavity represented
by the whole PCB, εr = 4.4 the relative permittivity of the
dielectric (FR4), µr= 1 the relative permeability of the PCB,
Le and We the effective dimensions of the PCB (10.3 cm

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SUBMITTED TO IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY3
square). λ0is the wavelength of the electromagnetic wave in
the PCB:
λ0=
n1f=
cc
√εrµrf
(10)
Dimensionless values p = 0.82 and c1 = 0.25 are computed
using Eq. 11 given in [6]:
p
=1 +a2
10(k0We)2+
5c2(k0Le)2+1
with a2= -0.16605, a4= 0.00761, c2= -0.0914153, and
1
n12+
It can be seen that Qradis inversely proportional to frequency.
4) Summary of losses: The overall quality factor for the
PCB and the integrated circuit is given by:
3
560(a22+ 2a4) (k0We)4+
70a2c2(k0We)2(k0Le)2
1
(11)
c1=
2
5 n14=
1
εrµr
+
2
5 (εrµr)2
(12)
1
Qf
=
1
Qc
+
1
Qd
+
1
Qrad
(13)
Table I illustrates the values of conductive, dielectric, radiated
and overall quality factors at various frequencies, which are
valid for the TM10cavity mode.
finj[MHz]
410
500
530
650
850
Qc
490.7
542
558
618
706.6
Qd
50
50
50
50
50
Qrad
4693
3847
3630
2960
2263
Qf
44.94
45.24
45.31
45.54
45.75
TABLE I
Q-FACTORS FOR POWER LOSSES
It can be seen that the lowest quality factors, corresponding to
the highest losses, are Qdand Qc. Therefore, only dielectric
and conductive losses will be modeled, since the DPI experi-
ment is valid up to 1 GHz.
B. Modeling of conductive and dielectric power losses
The objective of this study is to develop an electrical
simulation model for a complete DPI setup, making it possible
to use conventional SPICE-based simulators. This electrical
simulation thus requires equivalent electrical models for power
losses, which must be expressed as equivalent impedances.
The following section deals with the buildup of these equiva-
lent loss models.
In the DPI experiment, RF power is injected into a pin of the
IC by a feed port, which is modeled as a 0.2215 mil-sided
square [7]. Since the IC is located precisely at the center of
the PCB, and the dimensions of the IC package are relatively
small compared with the ones of the PCB, the injection point
can be considered to be located at the center of the PCB
by first approximation. Moreover, the spacing between both
planes of the PCB under test (1.6 mm) is much smaller than
the dimensions of the board (103 mm). Therefore, it can be
considered that the electromagnetic field propagates in a radial
direction outward from the source [4]. As a result, a circular
parallel plane structure made of imperfect conductors is used
(Fig.2).
Furthermore, a rectangular microstrip patch structure with an
electrically small w-wide current strip can be replaced by a
cylindrical current source with a radius equal to one-fourth of
w [6]. Then, the radius r0of this cylindrical current source is
equal to 0.02756 mils.
Fig. 2.
Discretization of power losses
This structure is discretized into an array of circular rings
with the same width ∆r, each circular ring representing one
segment of the proposed model. The equivalent impedance per
unit length Zc(r) of a ring is given in Eq. 14 ( [7], [8]):
Zc(r) =
1 + j
π σ δsr
(14)
in which r represents the radial distance from the injection
point, σ = 5.96 · 107S · m−1the conductivity of copper and
δsthe skin depth according to Eq. 7.
Zc(r) can be splitted into two equivalent devices Rc(r)
(resistance) and Lc(r) (inductance) in series given by Eq. 15
and 16:
1
π σ δsr=1
Rc(r) =
r
?µ0µr
?µ0µr
π σ
?
f
(15)
Lc(r) =
1
2π2f σ δsr=
1
2π rπ σ
1
√f
(16)
Then, the values of Rc(r) and Lc(r) are multiplied by ∆r in
order to obtain the whole model used for conductive losses.
This model is shown in Fig. 3.
Fig. 3.
losses
Equivalent electrical model of conductive and dielectric power
Dielectric losses can be modeled by a conductance shown in
Fig.3 and given by Eq. 17:
Gd(r) =2π ε0εrr tanδ
h
ω =4π2ε0εrr tanδ
h
f (17)

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SUBMITTED TO IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY4
As expected, it can be seen that dielectric losses are propor-
tional to frequency, even if the associated quality factor is a
constant. Above a given frequency, these dielectric losses can
prevail over conductive losses. It can be noted that the values
of these equivalent elements are frequency-dependent and thus
can not be modeled as plain resistors and inductors. Therefore,
behavioral electrical models (coded in VHDL-AMS) will be
used later in the simulation process.
IV. ELECTRICAL MODEL OF THE DPI SETUP
Since the evaluation of the immunity of the integrated circuit
under test requires an exact knowledge of the power actually
injected into the circuit, it is necessary to model the whole
DPI setup very accurately. Therefore, each part of the setup
(injection probe, injection capacitor, PCB, IC and directional
coupler) must be modeled separately as equivalent passive
elements; these individual models must then be combined in
order to obtain the whole equivalent model.
A. Modeling of the injection probe
The injection probe of a DPI setup is essentially a coaxial
cable with a copper core, but its impedance is not 50 Ω in
this case. Each part of the injection system (injection probe,
connection between the probe and the PCB ground) was mea-
sured and modeled separately from measurements obtained
with the help of a vector network analyzer (VNA). The model
of the injection probe is inductive, with a low series resistance.
This probe is attached to the IC under test through a capacitor
which will be modeled later, but its outer connector is soldered
on the ground plane of the PCB. Consequently, the inner
wire of the probe is coupled with the ground plane through
a capacitance and a resistance, representing the dielectric of
the coaxial cable. Moreover, the equivalent inductance of the
small wire connecting the core of the cable with the IC pin
is included in the model. Fig. 4 depicts a schematic of the
injection probe as well as its equivalent electrical model, while
Tab. II summarizes the actual values of its equivalent elements.
Fig. 4.
Schematic and equivalent model of the injection probe
Elements
L-probe-1
R-probe
R-probe-paras
Values
2.05 nH
1.06 Ω
300 Ω
Elements
L-probe-2
C-probe-coupl
Values
3.4 nH
0.85 pF
TABLE II
EQUIVALENT ELEMENTS OF THE INJECTION PROBE
B. Modeling of injection and decoupling capacitors
The DPI setup includes two discrete capacitors: a 1 nF
injection capacitor, used to prevent the reinjection of the DC
voltage supplied by the board into the RF power amplifier, and
a 47 nF decoupling capacitor located on the PCB. An accurate
impedance measurement of these capacitors can be achieved
thanks to an AgilentR
These ceramic SMD capacitors can be modeled by a series
RLC network. Fig. 5 plots the simulated, fitted impedance
profile of the injection capacitor, along with its equivalent
model.
?N1020A probe connected to a VNA.
Fig. 5. Impedance profile and equivalent model of the injection capacitor
The equivalent inductance can be computed from Eq. 18:
L =
1
4π2fres2C
(18)
in which fresis the resonant frequency of the capacitor.
The same operation can be reiterated for the decoupling
capacitor. The equivalent elements of both capacitors are
shown in Tab. III.
Elements
C-capa
R-capa
L-capa
Value
1.0 nF
0.12 Ω
0.8 nH
Elements
C-decoup
R-decoup
L-decoup
Value
47 nF
0.2 Ω
1.88 nH
TABLE III
EQUIVALENT ELEMENTS OF THE INJECTION AND DECOUPLING
CAPACITORS
Since the injection capacitor is soldered directly on the pin of

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SUBMITTED TO IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY5
the IC and the injection probe, no track length has to be taken
into account. Likewise, the decoupling capacitor is located
under the Vdd/Vss power pin pair of the IC, with less than
1 mm track length. This is included in the capacitor model.
C. Modeling of the PCB under test
In this study, the DPI setup does not follow the standard
proposal [1]. The custom-designed PCB (called ALI) (Fig. 6)
includes its own power supply, composed of a 9 V battery
and several regulators, including a 1.8 V regulator for the
digital core and IOs of the IC, the only one to be modeled in
this case. Conversely, the standard proposal requires the use
of an external power supply, with a choke inductor in series
preventing the reinjection of RF power into the supply. Since
most industrial boards include their own power supplies, this
case study may be closer to industrial requirements than the
typical DPI setup of the proposal. The key issue of the study
is that it can be supposed that a non-negligible amount of the
incident RF power is in fact injected into the power supply
of the board, and not in the IC or even in the decoupling
capacitor. This assertion will be demonstrated in Sect. VI-A.
The regulator, the battery and the PCB tracks (including vias)
were modeled by series RLC networks.In particular, the
Fig. 6.
ALI board (left: connector side, right: IC side)
inductances of the Vdd and Vss tracks, both located over a
ground plane, were established thanks to Eq. 19 [9]:
LVdd= LVss=µ0µrl
2 π
ln
?8h
w+w
4h
?
(19)
in which l and w are respectively the length and the width
of the track, h the distance between the track and the ground
plane. On this PCB, w = 300 µm and h varies between 0.5 mm
and 1.5 mm depending on the routing layer. Fig. 7 depicts the
whole model of the PCB, including the decoupling capacitor
modeled previously, while Tab. IV outputs the values of all
passive elements of the model.
It can be seen that the series inductance of the Vdd track
(including the regulator) is quite high. Therefore, the amount
of RF power injected into the power supply of the board should
decrease in high frequency. Likewise, the series inductance
of the decoupling capacitor should reduce the absorption of
RF power in high frequency. Consequently, more RF power
is supposed to be injected into the IC itself as frequency
increases.
Fig. 7.
decoupling capacitor
Model of the whole PCB and power supply, including the
Elements
C-decoup
R-decoup
L-decoup
R-battery
Values
47 nF
0.2 Ω
1.88 nH
30 mΩ
Elements
R-pcb-vdd
R-pcb-vss
L-pcb-vdd
L-pcb-vss
Values
0.196 Ω
0.016 Ω
62.35 nH
7.47 nH
TABLE IV
EQUIVALENT ELEMENTS OF THE WHOLE PCB AND POWER SUPPLY
D. Modeling of the integrated circuit
1) Introduction: The CESAME integrated circuit [10] was
designed at INSA Toulouse (France) and fabricated by ST
MicroelectronicsR
six logic cores, with a total of 610000 transistors. All cores are
identical from a functional point of view, however, they differ
in the design of their power supply architectures (plain, RC
decoupling, substrate isolation, meshed power supply rails).
2) Packagemodel:
CESAME
TQFP144 package. The electrical model of this package was
obtained from a 3D electromagnetic simulation with HFSSR
(AnsoftR
EMC2000R
model. The leftmost part of the model represents the lead-
frame, and the rightmost part represents the bonding and the
pads.
?in 0.18 µm technology. It is composed of
is encapsulated ina
?
?) [11] and verified at INSA Toulouse with ASERIS-
?(EADS-CCRR
?) [12]. Fig. 8 displays the whole
Fig. 8.
Package model
In order to compute the inductances of the leadframe and the
bonding, it can be noted that the Vddand Vsspins are adjacent
on the package, which implies that the current return path can
be easily determined. Therefore, their equivalent inductances