Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems

Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation
IEEE Transactions on Computers (Impact Factor: 1.47). 08/1982; DOI: 10.1109/TC.1982.1676056
Source: IEEE Xplore

ABSTRACT In a memory that uses byte-organized memory chips, each containing b (≥2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting–double byte error detecting codes (SbEC–DbED codes) are used in this kind of memory system to increase reliability.

1 Follower
  • [Show abstract] [Hide abstract]
    ABSTRACT: One of the objectives of coding theory is to ensure reliability of the computer memory systems that use high-density RAM chips with wide I/O data (e.g. 16, 32, 64 bits). Since these chips are highly vulnerable to m-spotty byte errors, this goal can be achieved using m-spotty byte error-control codes. This paper introduces the m-spotty Lee weight enumerator, the split m-spotty Lee weight enumerator and the joint m-spotty Lee weight enumerator for byte error-control codes over the ring of integers modulo ℓ (ℓ ≥ 2 is an integer) and over arbitrary finite fields, and also discusses some of their applications. In addition, MacWilliams type identities are also derived for these enumerators.
    Designs Codes and Cryptography 04/2014; 71(1). DOI:10.1007/s10623-012-9725-z · 0.73 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K bit DRAM's are organized in 32K × 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this correspondence we present a special decoding technique for double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.
    IEEE Transactions on Computers 01/1987; C-36(11):1359-1363. DOI:10.1109/TC.1987.5009476 · 1.47 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Cellular Automata (CA) is a novel approach for designing byte error-correcting codes. The regular, modular and cascaded structure of CA can be economically built with VLSI technology. In this correspondence, a modular architecture of CA based (32, 28) byte error correcting encoder and decoder has been proposed. The design is capable of locating and correcting all double byte errors. CA-based implementation of the proposed decoding scheme provides a simple cost effective solution compared to the existing decoding scheme for the Reed-Solomon (RS) decoder, having double error correcting capability.
    Industrial and Information Systems, 2008. ICIIS 2008. IEEE Region 10 and the Third international Conference on; 01/2008