Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems

Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation
IEEE Transactions on Computers (Impact Factor: 1.66). 08/1982; C-31(7):596 - 602. DOI: 10.1109/TC.1982.1676056
Source: IEEE Xplore


In a memory that uses byte-organized memory chips, each containing b (?2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting–double byte error detecting codes (SbEC–DbED codes) are used in this kind of memory system to increase reliability. A new class of SbEC–DbED codes is proposed. The proposed codes, differing from the Reed–Solomon codes, can be constructed for arbitrary code length and byte length b. Also, modularized SbEC–DbED codes, having encoding–decoding circuitries suitable for LSI implementation, are demonstrated. Optimal modularized SbEC–DbED codes, having k = 64, 128 bit data length, are derived for byte length b = 4 bit. Also, high-speed parallel encoding-decoding circuitries for the proposed codes are shown. Reliability improvement effects of the SbEC–DbED codes are clarified numerically in main memory units. Copyright © 1982 by The Institute of Electrical and Electronics Engineers, Inc.

1 Follower
22 Reads
  • Source
    • "All addresses and data are ECC protected, and they are checked and corrected at the input ports of LSI devices. 4-bit block correction and 4-bit double block detection (class of S4EC-S8/4ED [2]) are employed for data paths. If a correctable error is detected, the error is corrected, operation is not interrupted, and duplex operation is maintained. "
    [Show abstract] [Hide abstract]
    ABSTRACT: The PRIMEQUEST is an open architecture 32-way true-SMP server with powerful reliability features, which was designed and is manufactured by Fujitsu Limited. The PRIMEQUEST server was designed with a focus on high reliability and high performance. It incorporates processors of the Intel ® Itanium® processor family (IPF). We utilized rapidly improving silicon device technologies, specifically, high-density and high-speed technologies, in this system to obtain not only high performance but also high reliability. High-frequency data transfer technology, 90-nm silicon technology, and packaging technology providing high densities and optimized cooling were utilized in order to create a high performance system. We developed a new cache-state snooping method. With this method, both high-frequency operation and low-latency memory access even in a large-scale SMP are achieved. And flexible I/O functions are also realized. A system with 32 CPUs and 667-MHz DDR2 memory running at a system bus frequency of 1.3 GHz provides a memory bandwidth of 170 GB/s throughout the system. For high reliability, inter-chip and intra-chip connections are fully duplicated, and many checkers are properly integrated. These checking mechanisms ensure continuous operation by detecting faults and then disconnecting faulty parts and failed paths. We implemented this duplication extensively in the machines of the PRIMEQUEST series; the technology is called dual synchronous system architecture (DSSA). Our estimate of the resulting availability in a clustered system is 99.999%. 1.
  • Source
    • "Construction of codes correcting byte errors and properties of such codes are also studied. Some of the related work can be found in [2], [3]. However, the Lee metric was developed as an alternative to the Hamming metric for certain noisy channels that use phase-shift keying modulation [4]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Burst errors are very common in practice. There have been many designs in order to control and correct such errors. Recently, a new class of byte error control codes called spotty byte error control codes has been specifically designed to fit the large capacity memory systems that use high-density random access memory (RAM) chips with input/output data of 8, 16, and 32 bits. The MacWilliams identity describes how the weight enumerator of a linear code and the weight enumerator of its dual code are related. Also, Lee metric which has attracted many researchers due to its applications. In this paper, we combine these two interesting topics and introduce the m-spotty generalized Lee weights and the m-spotty generalized Lee weight enumerators of a code over Z q and prove a MacWilliams type identity. This generalization includes both the case of the identity given in the paper [I. Siap, MacWilliams identity for m-spotty Lee weight enumerators, Appl. Math. Lett. 23 (1) (2010) 13-16] and the identity given in the paper [M. \"Ozen, V. \c{S}iap, The MacWilliams identity for m-spotty weight enumerators of linear codes over finite fields, Comput. Math. Appl. 61 (4) (2011) 1000-1004] over Z2 and Z3 as special cases.
  • Source
    • "Construction of codes correcting byte errors and properties of such codes are also investigated. Some of the related work can be found in [3] [4] [2], etc. Recently, a MacWilliams identity has been proven for mspotty byte error codes [5]. "
    [Show abstract] [Hide abstract]
    ABSTRACT: It is a well established fact that m-spotty byte error control codes provide a good source for detecting and correcting errors in semiconductor memory systems using high-density RAM chips with wide I/O data (e.g. 8, 16 or 32 bits). Recently, a MacWilliams identity that establishes an important relation between an m-spotty weight enumerator of a binary code and its dual has been proven in Kazuyoshi Suzuki et al. (2007) [5]. In this paper, we introduce the m-spotty Lee weights and the m-spotty Lee weight enumerator of a quaternary code and prove a MacWilliams type identity.
    Applied Mathematics Letters 01/2010; 23(1-23):13-16. DOI:10.1016/j.aml.2009.07.019 · 1.34 Impact Factor
Show more