Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation IEEE Transactions on Computers
(Impact Factor: 1.66).
08/1982; C-31(7):596 - 602. DOI: 10.1109/TC.1982.1676056
In a memory that uses byte-organized memory chips, each containing b (?2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting–double byte error detecting codes (SbEC–DbED codes) are used in this kind of memory system to increase reliability. A new class of SbEC–DbED codes is proposed. The proposed codes, differing from the Reed–Solomon codes, can be constructed for arbitrary code length and byte length b. Also, modularized SbEC–DbED codes, having encoding–decoding circuitries suitable for LSI implementation, are demonstrated. Optimal modularized SbEC–DbED codes, having k = 64, 128 bit data length, are derived for byte length b = 4 bit. Also, high-speed parallel encoding-decoding circuitries for the proposed codes are shown. Reliability improvement effects of the SbEC–DbED codes are clarified numerically in main memory units. Copyright © 1982 by The Institute of Electrical and Electronics Engineers, Inc.
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