IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007935
An 11-Band 3–10 GHz Receiver in SiGe BiCMOS
for Multiband OFDM UWB Communication
Alberto Valdes-Garcia, Member, IEEE, Chinmaya Mishra, Student Member, IEEE,
Faramarz Bahmani, Member, IEEE, Jose Silva-Martinez, Senior Member, IEEE, and
Edgar Sánchez-Sinencio, Fellow, IEEE
Abstract—This work presents a receiver implementation for
MB-OFDM UWB communication that enables 11 bands of
operation covering 78% of the spectrum licensed by the FCC.
First, important system-level considerations are discussed with
basis on the specifications from the MB-OFDM standard. Next,
the different circuit techniques employed in the implementation
of the receiver are described. For the LNA design, a wideband
impedance match network that takes into account the package
components is introduced. A notch filter embedded in the LNA
and its tuning mechanism are proposed to attenuate the inter-
ference from devices operating in the U-NII band from 5.15
to 5.35 GHz. Based on the results of a recent investigation on
frequency planning for MB-OFDM radios, a compact 11-band
fast-hopping synthesizer implementation is proposed for the
receiver. The 264-MHz baseband section consists of a linear phase
low pass filter and a programmable gain amplifier; it presents an
in-band group delay variation of less than 0.6 ns and 42 dB of gain
in steps of 2 dB. The IC is fabricated in a 0.25- m SiGe BiCMOS
process, placed in a QFN package and mounted on FR-4 substrate
for its characterization. Measurement results show a receiver gain
of 78–67 dB and NF of 5–10 dB across the 11 bands from 3–10
GHz, while consuming 114 mA from a 2.5-V supply.
Index Terms—BiCMOS, direct conversion, frequency syn-
thesizer, multiband, notch filter, OFDM, radio frequency (RF),
receiver, SiGe, ultra-wideband (UWB), wideband matching.
respect to existent narrowband technologies, ultra-wideband
(UWB) achieves a high channel capacity and hence becomes
an attractive solution to the ever-increasing data rate demands
in the space of wireless personal area networks (WPAN).
The FCC regulations released in 2002 establish that UWB
Y SIGNIFICANTLY increasing the signal bandwidth [at
the expense of lower power spectral density (PSD)] with
Manuscript received August 25, 2006; revised December 19, 2006.
A. Valdes-Garcia was with the Analog and Mixed-Signal Center, Electrical
and Computer Engineering Department, Texas A&M University, College Sta-
ment, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA
C. Mishra, J. Silva-Martinez, and E. Sánchez-Sinencio are with the Analog
and Mixed Signal Center, Electrical and Computer Engineering Department,
Texas A&M University, College Station, TX 77843-3128 USA.
F. Bahmani was with the Analog and Mixed-Signal Center, Electrical and
Computer Engineering Department, Texas A&M University, College Station,
Digital Object Identifier 10.1109/JSSC.2007.892160
devices for communication applications can operate in the
unlicensed spectrum of 3.1–10.6 GHz while employing at least
500 MHz of bandwidth (measured at the frequency points
where the PSD has decreased by 10 dB) with a PSD of less
41.25 dBm/MHz .
(OFDM) modulation is an effective technique to capture mul-
tipath energy, achieve spectral efficiency and gain tolerance to
narrowbandinterferencesfor a veryhighdata rate(
system . This approach, known as Multiband OFDM (MB-
OFDM),has receivedstrongsupportfrom severalacademicand
commercial organizations and was approved as an industrial
standard in December 2005 . In this standard, the 7500-MHz
UWB spectrum is divided into 14 bands of 528 MHz each. The
bands are grouped into five band groups. Only the first group
of three bands, corresponding to the lower part of the spectrum
(3.1–4.8 GHz), is currently considered as mandatory. The re-
maining band groups have been defined and left as optional to
enable a structured and progressive expansion of the system ca-
pabilities. Current efforts from semiconductor companies for
the implementation of integrated UWB devices ,  focus
on this mandatory mode to achieve a fast time-to-market.
The use of three bands may be sufficient for current multi-
media applications with communication among few devices.
However, the accomplishment of the full potential of UWB
technology, the implementation of very high data rate WPANs
with multiple devices, demands radio implementations that can
use as many bands as possible. The allocated UWB spectrum
overlaps with Unlicensed National Information Infrastructure
(UNII) bands from 5.15–5.35 GHz and 5.725–5.825 GHz,
which are used by Wi-Fi devices. Due to their target appli-
cations, MB-OFDM and Wi-Fi radios will coexist in most
environments, preventing the effective use of a band group
that overlaps with the UNII band. Hence, 11 bands (four band
groups) is the maximum number that a practical MB-OFDM
UWB radio can cover.
This work presents an integrated and packaged wide-
band microwave system for MB-OFDM in SiGe BiCMOS.
Section II describes the proposed receiver architecture and the
system-level design considerations. Section III presents the de-
sign of the RF front-end building blocks including a 3–10-GHz
low-noise amplifier (LNA) with embedded notch filter and a
quadrature downconversion mixer. Section IV describes the
architecture and implementation of the 11-band fast-hopping
frequency synthesizer. The designs of the base-band building
0018-9200/$25.00 © 2007 IEEE
936IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
Fig. 1. Eleven-band 3–10-GHz direct-conversion receiver architecture.
blocks, namely the 264-MHz low-pass filter (LPF) and pro-
grammable gain amplifier (PGA) are discussed in Section V.
Section VI presents the measurement results from the IC
prototype. Finally, conclusions are drawn in Section VII.
II. RECEIVER ARCHITECTURE AND SYSTEM-LEVEL
Fig. 1 shows a block diagram of the implemented UWB
system . The RF front-end is fully differential; it presents
an input match to 50
for an off-chip antenna and provides
a nominal conversion gain of 35 dB. The LNA includes an
embedded notch-filter that provides an average attenuation
15 dB for frequencies in the low section of the 5-GHz
UNII band (5.15–5.35 GHz). The frequency of the notch is
guaranteed bya tuning mechanism implementedin thereceiver.
Note that the low section of the 5-GHz UNII band is the one
allows indoor transmissions in the U.S., Europe, and Japan .
The high section of the UNII band from 5.725–5.825 GHz is
considered for the 802.11a standard in the U.S. but only for
outdoor bridging  and will find less frequent interaction with
The receiver’s local oscillator (LO) is a fast-hopping fre-
quency synthesizer that generates 11 carrier tones according
to the band plan proposed in . Nevertheless, the presented
receiver chain is compatible with any other band plan that uses
bands of 528 MHz in the range of 3–10 GHz such as the one
from the MB-OFDM standard .
The third-order band-selection LPF is implemented by one
pole in the buffer at the output of the mixer and two poles by
a second-order Gm-C biquad. At the end of the receiver chain,
a PGA provides gain in the range of 0–42 dB that can be set
in steps of 2 dB through a digital control. The gain, frequency
response, and group-delay characteristics of the baseband sec-
tion are designed for a subsequent 1-GS/s ADC. A passive RC
rejects the DC offset at the output of the mixer. Since the first
(lower frequency) sub-carriers of the OFDM symbol are pilot
tones that do not carry any information , the spectral con-
tent suppressed by the HPF does not result in any performance
System-level simulations were performed to analyze the
effect of different receiver characteristics and non-idealities
on the bit-error-rate (BER) performance of the receiver. Fig. 2
shows a conceptual description of the macromodel built in Sys-
temVue  for this purpose. The model uses the OFDM symbol
parameters described in  for a 480-Mb/s data transmission
(highest rate) over an additive white Gaussian noise (AWGN)
channel. For the simulations, a quadrature phase-shift keying
(QPSK) constellation is considered for the individual sub-car-
riers. Sections II-A and B describe the system-level design
VALDES-GARCIA et al.: AN 11-BAND 3–10 GHz RECEIVER IN SiGe BiCMOS FOR MULTIBAND OFDM UWB COMMUNICATION 937
Fig. 2. Baseband equivalent system-level model for the receiver.
SUMMARY OF SPECIFICATIONS FOR THE PROPOSED MB-OFDM UWB RECEIVER AT 480 MB/s
consideratThe overall specification summary of the receiver
is outlined in Table I. The specifications for the frequency
synthesizer are derived and detailed in .
A. Receiver Gain, NF and Linearity
70.4 dBm for 480 Mb/s over AWGN . A noise figure
(NF) of about 9 dB is required under ideal system performance
taking into account the coding gain. A margin of 3 dB is
added to set the NF specification for the receiver as 6 dB. This
margin is defined after the evaluation of the degradation in
the demodulator performance due to the following combined
non-idealities: 1) 5 degrees in phase and 1 dB in amplitude
imbalance; 2) 4 bits of effective ADC quantization;
3) 5 dB of clipping in the signal peak-to-average ratio (PAR);
and 4) a signal-to-interference ratio (SIR) at baseband (due to
peer interference downconverted by spurs from the synthesizer)
of 15 dB.
to the input of the ADC (approximately equivalent to
) a receiver gain of 68 dB is required. The input match
and frequency response characteristics of the LNA limit its gain
to 15 dB. In order to relax the NF requirements from the base-
band LPF, the downconversion mixer gain is set to 20 dB for an
overall RF front-end conversion gain of 35 dB. The LPF pro-
vides 0 dB of gain across the passband. The maximum gain
from the PGA is set to 42 dB (9 dB higher than required for
a total receiver gain of 68 dB) to account for gain variations in
the front-end across the UWB spectrum and in order to support
the lower sensitivity levels required at lower data rates.
The MB-OFDM standard does not set specific interference
UWB signals, linearity specifications are set by the desired tol-
erance to the closest non-peer interferers which come from the
5-GHz ISM band. Input 1-dB compression point of
 and IIP3 of
9 dBm  have been proposed.
B. LPF and ADC Specifications
The use of OFDM modulation in a wideband communica-
tion system provides significant advantages such as spectral
efficiency and robustness to frequency selective channels and
narrowband interferers. However, due to the multipath charac-
teristics of an indoor channel, the individual sub-carriers from
the OFDM symbol may experience different delays, resulting
in the loss of orthogonality among them and BER degradation.
To counteract this effect, the symbol duration is extended for
a period of time known as the cyclic prefix. In the MB-OFDM
standard, the total symbol duration is 312.5 ns including a
cyclic prefix extension of 60.6 ns . The in-band group
delay variation across the analog portion of the radio receiver,
consumes a portion of the cyclic prefix and hence reduces the
overall system robustness against multipath.
Current MB-OFDM UWB receivers , ,  and 
employ high order (
5) and relatively sharp baseband filters to
938IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
Fig. 3. LNA circuit schematic.
implement all of the adjacent channel (centered 528 MHz away
necessary if the ADC has a sampling rate of 528 MHz. The im-
plementation of high order analog filters for the required signal
bandwidth (approx. 264 MHz) has the disadvantages of intro-
ducing a relatively large in-band group delay variation, large
area if a passive implementation is used , and increased
noise and power for an active implementation. In contrast, if
a 1.056-GS/s ADC follows the receiver, the 2X oversampling
ratio allows the implementation of linear phase filtering in the
digital domain. In this scenario, the required attenuation by the
analog filter is relaxed allowing an implementation with small
group delay variations. Hence, at the expense of power in the
peer interference is enhanced. The above-mentioned LPF and
ADC combination is chosen in the proposed system.
The LPF specifications are chosen to provide sufficient at-
tenuation to the alternate band (centered 1056 MHz away from
the band of interest) that transforms into an interferer due to
the aliasing from the ADC sampling. A third-order linear phase
Bessel filter achieves a group delay variation of less than 0.3 ns
(5% of the cyclic prefix) and attenuates the alternate band by
more than 30 dB. Since the OFDM modulation is inherently
robust to amplitude variations among the sub-carriers and the
rejection of the adjacent channel is implemented in the digital
domain, this receiver architecture is robust to variations in the
cut-off frequency of the LPF.
BER simulations show that a 4-bit quantization (including
5 dB of clipping in the peak to average ratio) to the OFDM
signal at 480 MB/s introduces a loss in sensitivity of only
0.1 dB. Therefore, to account for possible signal variations a
6-bit 1-GS/s ADC with 4–5 effective number of bits (ENOB)
up to 500 MHz is suitable for the MB-OFDM UWB system.
To clarify this trade-off in the increase of the ADC sample rate,
it is worth mentioning that a recently reported 6-bit ADC in
standard digital 0.13- m CMOS technology consumes 90 mW
at 600 MS/s and 160 mW at 1.2 GS/s .
III. RF FRONT-END IMPLEMENTATION
A. Wideband LNA Design
Attaining an input impedance match for the receiver in the
range of 3–10 GHz is particularly difficult if a relatively low-
cost package is used for the IC because its parasitics may domi-
nate the input impedance network. The circuit schematic of the
proposed UWB LNA for a packaged receiver is shown in Fig. 3
Afullydifferential topologyis chosentohavean inductancede-
generation value independent from the package
lation and reduce the Miller capacitance at the base of Q1–Q3,
which degrades the broadband impedance match. The base of
Q2 is tied to VDD so that Q1 has a collector to base voltage
greater than 500 mV which improves its
emitter length (50 m) and bias current (2.5 mA) for Q1 are set
to comply with the transconductance and capacitance require-
and low noise. Q2 has a smaller emitter length (10
reduce its parasitic capacitances. To attain a relatively flat gain
over the band of interest the R-L series load is designed taking
and linearity. The
VALDES-GARCIA et al.: AN 11-BAND 3–10 GHz RECEIVER IN SiGe BiCMOS FOR MULTIBAND OFDM UWB COMMUNICATION 939
Fig. 4. Simplified schematic of the input LC network.
into account the parasitics of the mixer and its interconnections
to the LNA.
A nMOS transistor is employed for the tail current because
of its reduced
requirement in comparison to the
a bipolar to remain in saturation. The parasitic capacitance
of the tail current transistor acts as a capacitive degeneration
to the input differential pair for common-mode signals. The
impedance transformation performed by the bipolar transis-
tors on this parasitic capacitance can trigger common-mode
oscillations. For this reason, the parasitic capacitance of the tail
current source should be minimized as much as possible.
The input matching network of the proposed LNA is an LC
bandpass filter structure formed by an inductively degenerated
differential pair, double bonding wires, lead frame capacitance
and the off-chip biasing components as shown in the circuit
schematic of Fig. 3. Even though the circuit is fully differential
and matched to 50
, the matching network can be analyzed as
single-ended circuit matched to 25
circuit model for this analysis is presented in Fig. 4. The induc-
tively degenerated bipolar transistor forms the resistive part of
the termination impedance. Overall, the structure approximates
a third-order Chebyshev LC bandpass filter . LW represents
the equivalent parallel inductance of two bonding wires with a
length of 1.5 mm each. An inductance of 1 nH/mm is assumed
ciated with the off-chip components are included in the model.
the matching network is the length of the bond wires (and thus
their inductance) since it depends on the final size and position
of the die within the package. For this reason the matching net-
work is designed to be as robust as possible to variations in LW.
Fig. 5 shows the calculated input reflection coefficient of Zin in
Fig. 4 with respect to 25
. After the design with the simpli-
fied model (Fig. 4), the matching network is implemented and
optimized at the schematic and post-layout levels taking into
account the additional components such as the bondpad’s ca-
pacitance and the transistor’s base resistance, which makes a
small contribution to the real part of the termination impedance.
Post-layout simulation results show a gain between 15 to 16 dB
from 2 to 9.8 GHz and NF
6 dB up to 10.3 GHz.
The LNA power consumption is 12.5 mW. A comprehensive
summary of recently reported LNAs designed for 3–10-GHz
. The proposed simplified
Fig. 5. Calculated input return loss for different bond wire inductance values.
operation is provided in . Comparable LNAs designed
for 3–10-GHz operation in a SiGe 0.18- m process have
reported power consumption in the range of 9.6–42.5 mW. In
this context, it can be concluded that this differential UWB
LNA designed for packaged operation also attains low power
B. Embedded Notch Filter
Another important challenge for a UWB LNA that is ad-
dressed in this design is the ability to reject the strong inter-
by a Q-enhanced LC series circuit that presents a very small
impedance at its resonant frequency. The circuit schematic is
shown in Fig. 6. At the frequency of interest for suppression,
the output current from the input differential pair is absorbed
by the notch filter instead of being converted into voltage at the
load. Degeneration resistors are used in the cross-coupled dif-
ferential pair to improve its linearity and prevent a degradation
of their effective negative conductance in the presence of large
interferers. A bank of discrete MIM capacitors is included to
provide tuning to the filter and compensate for possible process
variations. This tuning capacitance forms an overall third-order
filter structure with the series LC circuit. As shown in Fig. 6, an
nMOS transistor is used as a switch to have the bottom plates
of each pair of MIM capacitors either floating or connected to
each other at a virtual ground in differential mode. Additional
nMOS transistors and pull-up resistors are used to assure the
DC potential of the switch transistor’s channel and maximize
its on/off impedance ratio.
The proposed tuning mechanism exploits the resources al-
ready available in the receiver as shown in Fig. 7. In tuning
mode, a 5280-MHz test tone (provided by the frequency syn-
thesizer) is applied at the input of the series LC circuit with the
LO signal set at 4752 MHz. At baseband, the downconverted
test tone at 528 MHz shows the smallest amplitude for the cor-
rect control word set by the bits
notch covers all of the channels of the lower section of the UNII
,, and. Note that the
940IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
Fig. 6. Circuit schematic of the embedded tunable notch filter.
Fig. 7. On-chip tuning mechanism for the notch filter.
band,therefore, finetuning accordingto thespecific 802.11ain-
terference channel is not necessary.
A series LC resonant impedance at the output of a differential
pair has been used in the past for image rejection . In a nar-
the image frequency is not of major concern. In this case, how-
cies close to the interference frequency should not be affected.
This requirement sets a trade-off between the maximum achiev-
able interference rejection and the attenuation in the bands of
interest. After tuning, a gain suppression of around 15 dB is
achieved in the range of 5.15–5.35 GHz with a roll-off atten-
uation of less than 1 dB in the adjacent bands. Post-layout sim-
ulation results also show that the degradation in the NF outside
of the band of the notch is only 0.1 dB. The area overhead, with
respect to the LNA, is about 30% while the additional power
consumption is insignificant.
C. Quadrature Down-Conversion Mixer
Fig. 8 shows the quadrature downconversion mixer for
the UWB receiver. It is a fully differential Gilbert-cell based
and branches sharing the same RF input
stage. This eliminates the mismatch present in a downconverter
topology with separate
input transconductor is also improved in this mixer architecture
since the signal at the collector of the input transistors has a
frequency 4 times larger than the LO and hence has a small
The output current of the LO switching transistors is mir-
rored by pMOS transistors and converted to voltage in 2-k
resistor loads. This allows to maximize the achievable conver-
sion gain and output voltage swing without compromising the
overall mixer linearity. The voltage swing at the collector of the
LO switching transistors is small since this is a low-impedance
node. Current steering is used in the 1:1 current mirrors to re-
duce the bias current in the output stage. The NF overhead due
to the current mirrors is about 1 dB.
Four single-transistor buffers in the emitter-follower con-
figuration are employed to couple the differential quadrature
output from the mixer to the inputs of the second-order Gm-C
simulation results for the mixer show an overall voltage con-
version gain of 22 dB and NF of 15 dB both within 1 dB
variation across the range of 3–10 GHz while IIP3 varies from
5 to 3 dBm. These results correspond to a LO differential
amplitude of 100 mVp.
mixers. The linearity of the
IV. FAST-HOPPING 11-BAND FREQUENCY SYNTHESIZER
A. Frequency Synthesizer Architecture
A theoretical study on the choice of the frequency band plan
and synthesizer architecture for UWB was carried out in .
VALDES-GARCIA et al.: AN 11-BAND 3–10 GHz RECEIVER IN SiGe BiCMOS FOR MULTIBAND OFDM UWB COMMUNICATION 941
Fig. 8. Quadrature downconversion mixer circuit schematic.
Various architectures for UWB frequency synthesis were pro-
posed and evaluated with respect to their implementation com-
plexity and spur generation mechanisms. The synthesizer im-
plemented in this receiver derives its roots from the results of
that analysis. This efficient UWB synthesizer solution uses only
verters and multiplexers as shown in Fig. 1 to generate the 11
frequencies in quadrature from a single frequency source. The
generation of frequencies in the proposed architecture relies on
the fact that the fast band switching occurs between the bands
within a particular band group. The principle of operation in-
volves generating a reference tone
then obtaining the sidebands
The input frequency is chosen to be 8448 MHz as it results in
a compact architecture. In this implementation, the 8448-MHz
signal is applied externally and it forms the input to a phase
shifter results in
andphases of the signal at 8.448 GHz.
A VCO at 16 GHz followed by a divide by 2 or a quadrature
VCO at 8.448 GHz are other alternatives to generating the
and phases on chip. One of the phases of the 8.448-GHz
signal goes through a divide-by-2 circuit to result in 4224 MHz.
The 8448-MHz and 4224-MHz tones form the reference tones
in band groups 1 and 3, respectively. The 4224-MHz tone after
The tones at 528 MHz and 1056 MHz can serve as the clock for
the baseband ADC depending on its sample rate and architec-
ture. The tones at 4224 MHz and 1056 MHz are mixed in two
different SSB mixersto result in 3168 MHz and 5280 MHz (test
tone for notch tuning in LNA) tones. This particular configura-
tion results in equal loading at the outputs of the dividers by the
Furthermore, dummy dividers are placed at different stages to
in every band group and
528 MHz by single sideband
reduce imbalance between
for band group 2 and 4,
the 5th and 11th band frequencies, respectively), are generated
from the 8448 MHz tone
using (1) and (2).
andpaths. The reference tones
(that happen to be and
B. Building Blocks and Design Considerations
The RC-CR phase shifter is a first-order tunable network that
is implemented on-chip with a 100-
pacitor along with varactors to tune the cut-off frequency for
compensation of mismatch and process variations. A common
emitter buffer to compensate for the loss in the phase shifter, is
used to drive the rest of the circuits.
The divide-by-2 circuits are formed by two current-mode-
logic-based D-flip-flops in feedback. They ensure quadrature
phases at most of the frequencies. Careful layout considerations
have been taken to maintain the differential nature of the clocks
as well as to reduce the delay mismatch in the flip-flops.
The availability of quadrature signals from the divider chain
enables SSB mixing. Each mixer of the SSB mixer is based on
a Gilbert Cell without a tail current to save voltage headroom,
enabling operation of the bipolar transistors at peak
transistors are biased with current mirrors. The noise contribu-
tion of these mixers to the phase noise of the LO signal is min-
imal . Undesired variations in the signal, ground and supply
resistor and a 160-fF ca-
942IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
Fig. 9. LO buffer and multiplexer (only one path (???) shown).
Fig. 10. Third-order linear phase LPF architecture.
nodes are mitigated using filtering capacitors to ground and
maintaining layout symmetry among differential signals. Two
such SSB mixers are combined to result in quadrature outputs
at the sum or the difference of two frequencies. LC-tank-based
area and eliminate the need for tuning which would increase the
The multiplexers comprise of multiple cascode differential
pairs with a common resistive load. The final multiplexer/LO
buffer (Fig. 9) uses inductive peaking in the load to boost sig-
nals at higher frequencies providing relatively LO amplitude
over the entire range of frequencies at the input of the down
conversion mixer of the receiver. The digital bits
or disable the biasing to both the cascode transistors as well as
the tail current transistors. The band-hopping time is limited by
the switching time of the LO buffer or by that of the final SSB
quadrature mixer. For a band hopping taking place between the
extreme two tones in a band group (not involving the reference
tone) it is only the SSB mixer that switches from the upper side-
band to the lower sideband or vice versa. Post-layout simula-
tions show a maximum frequency hopping time of 5 ns.
V. BASEBAND CIRCUITS
A. Linear Phase LPF
The employed third-order structure is based on the
Bessel–Thompson approximation for
256 MHz; a block-level description is shown in
Fig. 10. The first pole, implemented by the buffer at the
output of the mixer, provides an attenuation of 5 dB at the
start of the downconverted alternate band (792 MHz offset)
while the Gm-C biquad provides additional 20 dB of sup-
pression at this frequency. The biquad’s design parameters
0.58 pF, and 1.18 pF. The
biquad and the common-mode feedback loop (CMFB) are
shown in Fig. 11. The
cell has been linearized by adding
andwhich operate in their linear region. The overall i–v
characteristic of the
cell can be approximately described as
cell used in the
represents the re-
. The OTA’s common-mode level is ad-
VALDES-GARCIA et al.: AN 11-BAND 3–10 GHz RECEIVER IN SiGe BiCMOS FOR MULTIBAND OFDM UWB COMMUNICATION 943
Fig. 11. ?
cell core and CMFB circuitry.
Fig. 12. PGA simplified circuit schematic.
justed by a high-speed CMFB block. To increase the speed of
the CMFB circuit, the load capacitance at each output has been
while the other component is attached to the common-mode ex-
provides the detection of fast common-mode signals, bypassing
the common-mode detection provided by the second
As a result, the CMFB block provides both suppression of high
frequency common-mode signals and good stability.
B. Programmable Gain Amplifier
The topology of the PGA is based on a source degenerated
input stage and programmable current mirrors, as shown in
Fig. 12. The P-type input stage presents smaller flicker noise
and enables the use of N-type programmable current mir-
rors. The input stage is optimized for linearity. The source
degeneration resistors are switched to change the overall
transconductance of the input stage providing the coarse gain
tuning (14 dB/step). Three gain steps provide gain variations
for 0, 14, and 28 dB. The fine gain tuning is obtained by using
Fig. 13. Chip microphotograph.
a programmable current mirror that employs a variable resistor
implemented by a transistor operating in triode region; it
944IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
Fig. 14. UWB receiver test board.
is connected at the source of a diode connected transistor and
its value is controlled via
the output through
For small signal variations the current gain is approximately
gate voltage of the triode connected transistor
rent gain factor is then adjusted. The programmable current
mirror is able to provide enough linearity if the ratio of the DC
current to the peak value of the AC current is large enough;
e.g., it can be shown mathematically that IM3
. Since the bias current of the N-type
output transistors (associated with
rent-gain control voltage, it has to be removed at the PGA’s
output.Acopy ofthecurrentofthetwobranchesis injectedinto
a 2:1 P-type current mirror to generate the DC current
and mirrored to PGA’s output; therefore,
lowing stages. Device mismatch will add some small DC offset,
which is not critical since the PGA has a resistive load and its
output can be AC coupled to the ADC. The programmable cur-
rent mirror provides a gain range of 0–12 dB with a resolu-
tion of 2 dB/step. The combination of the programmable input
stage and the current mirror leads to an overall 0–40 dB pro-
grammable gain in steps of 2 dB.
. The current is mirrored to
; by properly controlling the
40 dB if
) varies with the cur-
VI. EXPERIMENTAL RESULTS
The proposed UWB receiver is implemented in the IBM 6HP
0.25- m BiCMOS process. Fig. 13 shows the microphotograph
of the IC prototype. The total employed area including pads
is 5.6 mm . All of the measurement results presented in this
(QFN) package mounted on a standard FR-4 substrate. Other
more expensive packaging and PCB materials exhibit better
properties at these frequencies; nevertheless, the mentioned
materials were chosen to show the feasibility of a low-cost
solution. Fig. 14 shows the receiver module’s PCB photo. The
calibration plane for all of the measurements was placed at the
SMA connectors, the loss and frequency response of the PCB
traces was not de-embedded to measure the performance of the
receiver module as it would be seen from an antenna mounted
on the PCB.
A. Receiver Input Impedance Match
The fabricated circuits are fully differential while the em-
ployed network analyzer supports only single-ended ports. To
perform differential measurements, the use of a balun is re-
quired. Commercial baluns that operate in this frequency range
show a typical attenuation of 8 dB. This attenuation can sig-
nificantly alter the s-parameter measurements, especially in the
case of the S11 test. For this reason, it was decided to perform
the measurements in a single-ended way, by connecting one of
the inputs of the LNA to ground.
The measured S11 response is shown in Fig. 15. With the
exception of a small region at 6.2 GHz (pointed by the mea-
surement marker), the input match is better than
3.4 to 11 GHz. Between approximately 7.5 and 10.5 GHz the
input match is better than
15 dB, which is better than what
was expected from simulations. This is the result of having the
bond wires shorter than their expected nominal value and an in-
creased power loss in the PCB for frequencies beyond 7 GHz.
10 dB from
B. Notch Filter
The receiver’s LNA followed by a wideband buffer was also
fabricated and packaged separately. Fig. 16 shows the S21 mea-
the frequency response and tuning behavior of the notch filter.
Only five of the eight possible frequency responses (each corre-
VALDES-GARCIA et al.: AN 11-BAND 3–10 GHz RECEIVER IN SiGe BiCMOS FOR MULTIBAND OFDM UWB COMMUNICATION 945
Fig. 15. Measured receiver input match.
Fig. 16. Measured frequency response of the notch filter for different tuning
Attenuation higher than 10 dB is achieved over a bandwidth
of 200 MHz (5.15–5.35 GHz) with peak attenuation of 20 dB,
meeting the design goals. The same attenuation was observed at
around the frequency of the notch.
C. Frequency Synthesizer
For the frequency spectrum characterization, the input at
8448 MHz was provided from a signal generator followed by a
wideband balun to provide the differential input into the chip.
Fig. 17 shows the single-ended output of the frequency synthe-
sizer at 10.032 GHz. A significant leakage of the 8448-MHz
input tone to the synthesizer test output occurs due to PCB
coupling. However, this tone has an insignificant leakage to
Fig. 17. Measured output spectrum for band#11.
Fig. 18. Receiver band switching at baseband (LO switch from 3.696 GHz to
the internal LO port of the downconversion mixer. The mea-
sured spurs at in-band frequencies for all frequency bands up
to 8.5 GHz are better than
18 dBc, which is tolerable in a
MB-OFDM system according to the analysis presented in .
For frequencies greater than 8.5 GHz, the filtering effect of
the bond wire and package, and the loss in PCB (post layout
simulations with estimated parasitics indicate an attenuation
of more than 10 dB for frequencies beyond 9 GHz) reduce the
power level of the desired tone and hence the rejection of spurs
at lower frequencies appears to be lower.
D. Receiver Band-Hopping
While the switching speed of the synthesizer is important, a
more meaningful performance metric is how fast the commu-
tation between two adjacent bands is perceived at the baseband
of the receiver. To perform this test the RF input to the LNA
was fixed at 4.124 GHz and the LO frequency was switched
946IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
MEASURED PERFORMANCE PER BAND-GROUP
DISTRIBUTION OF CURRENT CONSUMPTION AND AREA
Fig. 19. Receiver frequency response.
from 3.696 GHz to 4.224 GHz resulting in a baseband output
switching from 428 MHz to 100 MHz, respectively. This is
shown in Fig. 18.
E. Receiver Baseband Frequency Response
Within a range of 500 MHz, the frequency response from the
LNA input to the current output of the RF transistors from the
downconversion mixer is expected to remain essentially con-
stant. The frequency response of the receiver within a given
quency is swept across 450 MHz (e.g., 4224–4674 MHz) and
the receiver’s output is measured with a spectrum analyzer. The
resultant frequency response is shown in Fig. 19. The observed
variations are mainly due to changes in the amplitude of the RF
ulated frequency response from the output of the downconver-
Fig. 20. Measured group delay variation of the LPF.
the pass band, which is also in good agreement with the simu-
F. Receiver Chain Gain, Linearity, and NF
In the MB-OFDM approach, subsequent bits of information
are spread across the three bands of the band group in use.
against fading, interference and receiver non-idealities. For this
reason, from the point of view of the complete communication
system, the relevant performance of the receiver is its average
behavior across the band group. Table II presents a summary
of the measured results for each band group. The input 1-dB
compression is measured at a gain of 0 dB in the PGA. The
measured out-of-band IIP3 for the first band group is
This is the worst-case linearity since the front-end gain reduces
at higher frequencies. Table III details the current consumption
and area per building block. The degradation in the NF and gain
of the receiver for the last two band groups is attributed to the
following two factors: 1) the PCB loss at the input of the re-
ceiver which is also reflected in the improvement of the input
match and the 1-dB compression point at these frequencies, and
2) a reduction in the LO amplitude at the input of the down-
conversion mixer due to the effects of process variations on the
VALDES-GARCIA et al.: AN 11-BAND 3–10 GHz RECEIVER IN SiGe BiCMOS FOR MULTIBAND OFDM UWB COMMUNICATION947
SUMMARY OF CURRENT STATE-OF-THE-ART IN MB-OFDM UWB RECEIVERS
Includes current consumption of the transmitter
Without current consumption of a VCO
frequency response of the wideband LO buffer at the output of
the frequency synthesizer.
An integrated receiver for MB-OFDM UWB communication
operating in the range of 3–10 GHz has been demonstrated.
Important challenges for the practical use of UWB receivers
on-chip rejection of interference in the range of 5.15–5.35 GHz
substrate. To place the achieved results in perspective, Table IV
presents a summary of the currently reported MB-OFDM UWB
radios. This receiver IC demonstrates the feasibility of low cost
and very high data rate radios capable of maximizing the use of
the available UWB spectrum. To the best of the authors’ knowl-
edge this is the first published 3–10-GHz MB-OFDM UWB re-
ceiver and the first published UWB receiver operating beyond
5 GHz demonstrated in package.
The authors thank Mr. L. Chen for the design of the
PGA, Mr. X. Fan for technical discussions, Dr. A. Batra, Dr.
J. Balakrishnan, Dr. N. Belk, and Dr. A. F. Mondragon-Torres
from the DSPS Research and Development Center of Texas
Instruments, Dallas, for helpful discussions, the RF Wireless
Group of Texas Instruments, Dallas, for testing facilities, and
the MOSIS Service for the fabrication of the IC prototype.
 First Report and Order, Revision of Part 15 of the Commission’s Rules
Regarding Ultra-Wideband Transmission Systems FCC, 2002, ET
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“Design of a multiband OFDM system for realistic UWB channel en-
vironments,” IEEE Trans. Microwave Theory and Tech., vol. 52, no. 9,
pp. 2123–2138, Sep. 2004.
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ECMA standard 368.
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Kang, C.-C. Hsu, and C.-C. Lee, “A UWB CMOS transceiver,” IEEE
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van de Beek, G. van der Weide, H. Waite, Y. Zhang, S. Aggarwal, and
C. Razzell, “An interference-robust receiver for ultra-wideband radio
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receiverin 0.25 ?m SiGe BiCMOS,” in Symp. VLSI Circuits Dig. Tech.
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Sinencio, and J. Silva-Martinez, “Frequency planning and synthesizer
architectures for multiband OFDM UWB radios,” IEEE Trans. on
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Alberto Valdes-Garcia (S’00–M’06) received the
B.S. degree in electronic systems engineering from
the Monterrey Institute of Technology (ITESM),
Campus Toluca, Mexico, in 1999 (highest honors as
best score from all majors), and the Ph.D. degree in
electrical engineering from Texas A&M University,
College Station, in 2006.
In 2000, he was a Design Engineer with Motorola,
Broadband Communications Sector. From 2001 to
2004, he was a Semiconductor Research Corporation
(SRC) research assistant at the Analog and Mixed-
948IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007 Download full-text
Signal Center (AMSC), Texas A&M University. In the summer of 2002, he was
storage applications. In the summer of 2004, he was with IBM Research, where
he worked on the analysis and design of 60-GHz SiGe power amplifiers. His
doctoral research work covered system-level, ADC and RF circuit design for
for analog and RF circuits. Since January 2006, he has been working as a Re-
search Staff Member with the Communication Technologies Department, IBM
T. J. Watson Research Center. His present researchwork is on silicon integrated
millimeter-wave communication systems. He is a coauthor of the book Test and
Diagnosis of Analogue and Mixed-signal Integrated Circuits (IET, 2007).
Dr. Valdes-Garcia was the recipient of a scholarship from the Mexican Na-
is the winner of the 2005 Best Doctoral Thesis Award presented by the IEEE
Test Technology Technical Council (TTTC).
Chinmaya Mishra (S’03) received the B.E. (Hons.)
degree in electrical and electronics engineering from
Birla Institute of Technology and Science, Pilani,
India, in 2002, and the M.S. degree in electrical
engineering from Texas A&M University, College
Station, in 2004. He is currently working toward the
Ph.D. degree at the Analog and Mixed Signal Center
(AMSC), Texas A&M University.
In the spring of 2002, he was a technical intern
in the DSP Design Group at Texas Instruments Inc.,
Bangalore, India, where he worked on formal verifi-
cation of hardware circuits. During the summer of 2005, he was a RF IC Design
Engineer (intern) at WiQuest Communications Inc, Allen, TX, where he was
responsible for the design of a CMOS frequency synthesizer for a UWB radio.
In the spring and summer of 2006, he was with the Communications Circuits
and Systems Department at the IBM T. J. Watson Research Center, Yorktown
and CMOS technologies. His current research interests include RF circuit de-
sign for broadband wireless systems.
Mr. Mishra received the IEEE Solid-State Circuits Society Predoctoral Fel-
lowship for 2006–2007.
Faramarz Bahmani (S’01) received the M.Sc.
(Hons.) degree in electronics engineering from
Tehran University, Tehran, Iran, and the Ph.D.
degree in electrical engineering from Texas A&M
University, College Station, in 1999 and 2006,
From 1999 to 2001, he was a Senior Design
Engineer with Emad Semiconductors, Tehran, Iran,
where he worked on high-speed analog circuit
design. During the summer of 2005, he interned as
a Circuit Design Engineer at Alvand Technology
Inc., Santa Clara, CA, where he designed a wideband CMOS frequency
synthesizer for video applications. He is currently with Scintera Networks
Inc., San Jose, CA, developing high-frequency CMOS clock and data recovery
circuits. His research interests include high-speed analog and RF circuits,
phase-locked-loop-based frequency synthesizers, and highly linear contin-
José Silva-Martínez (SM’98) was born in Teca-
B.S. degree in electronics from the Universidad
Autónoma de Puebla, México, in 1979, the M.Sc.
degree from the Instituto Nacional de Astrofísica
Optica y Electrónica (INAOE), Puebla, México, in
1981, and the Ph.D. degree from the Katholieke
Univesiteit Leuven, Leuven, Belgium, in 1992.
From 1981 to 1983, he was with the Electrical
Engineering Department, INAOE, where he was
involved with switched-capacitor circuit design.
In 1983, he joined the Department of Electrical Engineering, Universidad
Autónoma de Puebla, where he remained until 1993. He was a co-founder
of the graduate program in opto-electronics in 1992. From 1985 to 1986, he
was a Visiting Scholar in the Electrical Engineering Department, Texas A&M
University. In 1993, he re-joined the Electronics Department, INAOE, and from
May 1995 to December 1998, was the Head of the Electronics Department; He
was a co-founder of the Ph.D. program on Electronics in 1993. He is currently
with the Department of Electrical Engineering, Analog and Mixed Signal
Center, Texas A&M University, College Station, where he holds the position of
AssociateProfessor.Hiscurrentfield ofresearchisin the designandfabrication
of integrated circuits for communication and biomedical application.
Dr. Silva-Martínez has served as IEEE CASS Vice President Region-9
(1997–1998) and as Associate Editor for IEEE Transactions on Circuits and
Systems part-II from 1997–1998 and 2002–2004, and for TCAS-I since 2004.
He was the main organizer of the 1998 and 1999 International IEEE CAS
Tour in region 9, and Chairman of the International Workshop on Mixed-Mode
IC Design and Applications (1997–1999). He is the inaugural holder of the
TI Professorship-I in Analog Engineering, Texas A&M University. He was a
co-recipient of the 1990 European Solid-State Circuits Conference Best Paper
Edgar Sánchez-Sinencio (M’74–SM’83–F’92) was
born in Mexico City, Mexico. He received the degree
in communications and electronic engineering (Pro-
fessional degree) from the National Polytechnic In-
stitute of Mexico, Mexico City, the M.S.E.E. degree
from Stanford University, CA, and the Ph.D. degree
in 1966, 1970, and 1973, respectively.
In 1974, he held an industrial Post-Doctoral posi-
tion with the Central Research Laboratories, Nippon
to 1983, he was the Head of the Department of Electronics at the Instituto
Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He
was a Visiting Professor in the Department of Electrical Engineering at Texas
A&M University, College Station, during the academic years of 1979–1980 and
1983–1984. He is currently the TI J. Kilby Chair Professor and Director of the
Analog and Mixed-Signal Center at Texas A&M University. He is a coauthor
of the book Switched Capacitor Circuits (Van Nostrand-Reinhold, 1984), and
coeditor of the book Low Voltage/Low-Power Integrated Circuits and Systems
(IEEE Press, 1999). His current interests are in the area of RF-communication
circuits and analog and mixed-mode circuit design.
Dr. Sánchez-Sinencio was an Associate Editor for IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS from 1985 to 1987, and an Associate Editor for the
IEEE TRANSACTIONS ONNEURAL NETWORKS. He is the former Editor-in-Chief
of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He is a former
IEEE CAS Vice President-Publications. He was the General Chairman of the
1983 26th Midwest Symposium on Circuits and Systems. In November 1995,
he wasawarded an Honoris CausaDoctorate by the National Institutefor Astro-
physics, Optics and Electronics, Mexico, the first honorary degree awarded for
microelectronic circuit design contributions. He was a co-recipient of the 1995
Guillemin–Cauer award for his work on cellular networks. He was also a co-re-
cipient of the 1997 Darlington Award for his work on high-frequency filters. He
received the Circuits and Systems Society Golden Jubilee Medal in 1999. He
was the IEEE Circuits and Systems Society Representative to the Solid-State
Circuits Society during 2000–2002. He was a member of the IEEE Solid-State
Circuits Society Fellow Award Committee from 2002 to 2004. He is currently
a member of the IEEE CAS Society Board of Governors.