1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

Sch. of Electr. Eng., Univ. of Ulsan, South Korea
IEEE Journal of Solid-State Circuits (Impact Factor: 3.11). 07/2004; DOI: 10.1109/JSSC.2004.827795
Source: IEEE Xplore

ABSTRACT A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-μm standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dBΩ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-μA average input noise current, -17-dBm sensitivity for 10-12 bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.

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    ABSTRACT: A transimpedance amplifier (TIA) has been designed in a 0.35 μm digital CMOS technology for Gigabit Ethernet. It is based on the structure proposed by Mengxiong Li [1]. This paper presents an amplifier which exploits the regulated cascode (RGC) configuration as the input stage with an integrated optical receiver which consists of an integrated photodetector, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. A series inductive peaking is used for enhancing the bandwidth. The proposed TIA has transimpedance gain of 51.56 dBΩ, and 3-dB bandwidth of 6.57 GHz with two inductor between the RGC and source follower for 0.1 pF photodiode capacitance. The proposed TIA has an input courant noise level of about 21.57 pA/Hz0.5 and it consumes DC power of 16 mW from 3.3 V supply voltage.
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    ABSTRACT: Purpose ‐ The purpose of this paper is to design a very low-noise transimpedance amplifier (TIA) for a novel multi-pixel CMOS photon detector which performs secondary electron (SE) detection in the scanning electron microscope (SEM). Design/methodology/approach ‐ The TIA, which is implemented with three-stage push-pull inverters, is optimised using a nomograph technique developed in MATLAB. SPICE simulations are conducted to verify the results generated from MATLAB. Important performance figures are obtained experimentally and these measurements are compared with simulation results. Findings ‐ A low-noise TIA fabricated in a standard 0.35?µm CMOS technology was tested. Experimental results obtained show that the TIA connected to a photodiode with a junction capacitance of 0.8?pF can carry out its task effectively with a transimpedance gain of 126.9?dBO, a bandwidth of 9.8?MHz, an input-referred noise of 2.50×10-13 A/vHz and an SNR of 12.8. The power consumption of the TIA was 49.3?mW. These encouraging results have exhibited the potential of the circuit for use in the CMOS photon detector. Originality/value ‐ This paper presents a low-noise transimpedance amplifier that is highly suitable to be used as a critical constituent block for the CMOS photon detector which aims to take over the role of photomultiplier tube in SE detection in the SEM. Solid-state approaches have recently been reinvigorated for improving certain aspects of SE detection in scanning electron microscopy and this work has supported and contributed to the trend.
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