1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects
ABSTRACT A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-μm standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dBΩ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-μA average input noise current, -17-dBm sensitivity for 10-12 bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.
Conference Paper: High bandwidth 0.35μm CMOS transimpedance amplifier[Show abstract] [Hide abstract]
ABSTRACT: A transimpedance amplifier (TIA) has been designed in a 0.35 μm digital CMOS technology for Gigabit Ethernet. It is based on the structure proposed by Mengxiong Li . This paper presents an amplifier which exploits the regulated cascode (RGC) configuration as the input stage with an integrated optical receiver which consists of an integrated photodetector, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. A series inductive peaking is used for enhancing the bandwidth. The proposed TIA has transimpedance gain of 51.56 dBΩ, and 3-dB bandwidth of 6.57 GHz with two inductor between the RGC and source follower for 0.1 pF photodiode capacitance. The proposed TIA has an input courant noise level of about 21.57 pA/Hz0.5 and it consumes DC power of 16 mW from 3.3 V supply voltage.Complex Systems (ICCS), 2012 International Conference on; 01/2012
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ABSTRACT: With ever increasing network traffic, dynamic load balancing can achieve improved performance in a typical distributed system to cope with the fluctuating workload. The hybrid dynamic load balancing algorithm stays away from the drawbacks of centralized and decentralized load balancing approaches. In this paper, first we address the two imperative design issues that are crucial to the hybrid algorithm viz. division of distributed nodes into virtual groups (clusters) and cluster head (supernode) selection in each group. We propose a new strategy for clustering of nodes based on the theory of integer partition. We deal with supernode selection in each group by proposing two novel algorithms that describe the tradeoff between message complexity and performance. Subsequently, we evaluate the performance of the hybrid algorithm in heterogeneous distributed system. We observe that our hybrid algorithm potentially outperforms the classical decentralized load balancing algorithm.Parallel Distributed and Grid Computing (PDGC), 2012 2nd IEEE International Conference on; 01/2012
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ABSTRACT: Purpose ‐ The purpose of this paper is to design a very low-noise transimpedance amplifier (TIA) for a novel multi-pixel CMOS photon detector which performs secondary electron (SE) detection in the scanning electron microscope (SEM). Design/methodology/approach ‐ The TIA, which is implemented with three-stage push-pull inverters, is optimised using a nomograph technique developed in MATLAB. SPICE simulations are conducted to verify the results generated from MATLAB. Important performance figures are obtained experimentally and these measurements are compared with simulation results. Findings ‐ A low-noise TIA fabricated in a standard 0.35?µm CMOS technology was tested. Experimental results obtained show that the TIA connected to a photodiode with a junction capacitance of 0.8?pF can carry out its task effectively with a transimpedance gain of 126.9?dBO, a bandwidth of 9.8?MHz, an input-referred noise of 2.50×10-13 A/vHz and an SNR of 12.8. The power consumption of the TIA was 49.3?mW. These encouraging results have exhibited the potential of the circuit for use in the CMOS photon detector. Originality/value ‐ This paper presents a low-noise transimpedance amplifier that is highly suitable to be used as a critical constituent block for the CMOS photon detector which aims to take over the role of photomultiplier tube in SE detection in the SEM. Solid-state approaches have recently been reinvigorated for improving certain aspects of SE detection in scanning electron microscopy and this work has supported and contributed to the trend.Microelectronics International 07/2013; 30(3). · 0.87 Impact Factor
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004971
1-Gb/s 80-dB? Fully Differential CMOS Transimpedance Amplifier in
Multichip on Oxide Technology for Optical Interconnects
Sung Min Park, Member, IEEE, Jaeseo Lee, and Hoi-Jun Yoo, Member, IEEE
Abstract—A 1-Gb/s differential transimpedance amplifier
(TIA) is realized in a 0.25- m standard CMOS technology,
incorporating the regulated cascode input configuration. The TIA
chip is then integrated with a p-i-n photodiode on an oxidized
phosphorous-silicon (OPS) substrate by employing the multi-
chip-on-oxide (MCO) technology. The MCO TIA demonstrates
80-dB? transimpedance gain, 670-MHz bandwidth for 1-pF
photodiode capacitance, 0.54- A average input noise current,
17-dBm sensitivity for 10
power dissipation from a single 2.5-V supply. It also shows
negligible switching noise effect from an embedded VCO on the
OPS substrate. Furthermore, a four-channel MCO TIA array
is implemented for optical interconnects, resulting in less than
40-dB crosstalk between adjacent channels.
??bit-error rate (BER), and 27-mW
oxidized phosphorous-silicon (OPS), regulated cascode, switching
noise, transimpedance amplifier (TIA).
viding low-power and low-cost solutions.However, it exhibits
inherent substrate coupling noise between high-fidelity analog
circuits and noisy digital logic. As the operating frequency (or
bit rate) increases, the substrate noise becomes very severe
and significantly deteriorates the system signal-to-noise ratio
(SNR) or bit-error rate (BER). Gigabit optical receivers are a
Fig. 1 illustrates an optical receiver system, which consists
of a transimpedance amplifier (TIA), a post-amplifier, a clock
and data recovery circuit with an embedded voltage-controlled
oscillator (VCO), and a digital demultiplexer. Among these
blocks, the front-end analog TIA is the most critical and sensi-
tive element in terms of noise. Therefore, the design mandates
careful optimization not only to minimize the amplifier noise
itself, but also to reduce the switching noises from digital
circuitry coupled through common substrate.
In general, differential configurations provide better immu-
nity to common-mode noises, such as power supply noise or
of design challenges exist in the differential configurations,
particularly for optical front-end TIA designs. First, a dummy
high-speed analog and digital circuits in a single chip, pro-
Manuscript received November 6, 2002; revised February 20, 2004.
Ulsan 680-749, Korea. He is now with the Department of Information Elec-
tronics Engineering, Ewha Womans University, Seoul 120-750, Korea (e-mail:
J. Lee and H.-J. Yoo are with the Department of Electrical Engineering and
Computer Science, Korea Advanced Institute of Science and Technology, Dae-
jeon 305-701, Korea.
Digital Object Identifier 10.1109/JSSC.2004.827795
Fig. 1.Overview of optical receiver system.
capacitor, which is often added to the negative input to balance
the photodiode capacitance , is not cost or size effective,
especially when considering the applications of parallel optical
interconnects. Second, the chip layout requires very careful
matching in order to minimize the offset. Third, differential
circuits dissipate almost twice the power and yield nearly 3
dB worse noise than single-ended. Nevertheless, differential
configurations are adopted in this work since the need of a
dummy capacitor can be efficiently avoided by incorporating
the current-mode regulated cascode (RGC) circuit technique
–. Also, a multichip-on-oxide (MCO) technique is
employed as a multichip module (MCM) in order to relax the
substrate coupling noise effect.
Section II describes the mechanism of the RGC input and
the design of a differential RGC TIA. The measured results of
the RGC TIA in the MCO technology and the digital switching
noise effect on the analog TIA are discussed in Section III.
II. DIFFERENTIAL REGULATED CASCODE TIA
It is well known that tradeoffs between bandwidth and
photodiode capacitance are inevitable in a conventional
common-source TIA. Even though common-gate (CG) input
configuration helps a TIA to relax the tradeoffs, it cannot yet
effectively isolate the large photodiode capacitance from the
bandwidth determination because of small
transistor. Meanwhile, the RGC input configuration reported
in – enhances the input
feedback mechanism, so that the RGC TIA can achieve better
isolation of the photodiode capacitance than other configura-
tions. Namely, the RGC circuit enables the TIA to avoid the
need of a dummy input capacitor due to the virtual-ground
input impedance, thus facilitating the realization of an optical
interconnect system in a single chip. Also, the virtual ground
input reduces the noise coupling from
todiode into the TIA so much that there is no longer a need to
balance it out. Furthermore, proper sizing of the local feedback
stage reduces the dominant high-frequency noise contribution
of the RGC TIA without deteriorating the stability .
of the input
significantly due to the local
through the pho-
0018-9200/04$20.00 © 2004 IEEE
972IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004
Fig. 2.Schematic diagram of a differential regulated cascode TIA.
Fig. 2 shows the schematic diagram of a differential RGC
TIA, which comprises the RGC input stage, the second
voltage-gain stage with threshold-voltage loss compensation
(TLC) loads , and the output buffer with shunt-peaking
inductor loads. In the TLC loads, each pMOS
cross-connected to source followers
Thereby, the threshold-voltage
compensated and the output voltage at drains can swing up to
. If, the pMOS loads operating in ohmic
region result in small signal resistance of
The feedback resistor
is applied to the drain of
to the efficient current buffer operation of the RGC input . It
is also fed back from the drain of
at low supply voltages and to ac-
quire broadband and low crosstalk characteristics by reducing
the node impedance . The short feedback loop would reduce
the group-delay variation and thus improve the jitter character-
istic of the amplifier. The
is implemented by a linear-mode
pMOS in this work.
The output buffer consists of a dc level-shifter and a current-
the dc levels but also to boost the voltage gain further. Since
the level-shifter may reduce the bandwidth, inductive peaking
technique is incorporated at the CML output stage in order to
compensate the possible reduction of the bandwidth .
This work shares the basic configuration with the previous
single-ended RGC TIA in , and thus, the
is approximately given by
loss of the pMOS loads is
, which helps to achieve
is the parasitic capacitance of the feedback resistor, and
the output conductance of
is the drain capacitance of
,is the gate
Noise analysis shows that the equivalent noise current spec-
tral density is approximately given by
parasitic capacitance including photodiode capacitance, ESD
protection diode capacitance, and bond-pad parasitic capaci-
The minimum noise current of the TIA is obtained by sat-
isfying three conditions: 1)
; and 3)
,, andare designed to be 45
m, respectively. Yet, further optimization is necessary to
achieve proper power allocation between the RGC input stage
and the second voltage-gain stage, thereby improving the sensi-
tivity and bandwidth performance.
is the Boltzmann constant,
is the noise factor of the MOSFET,
is the absolute temper-
is the input
,is the source–bulk
is the drain capacitance of the
. Here, the gate widths
m, 100m, and
III. MEASURED RESULTS OF DIFFERENTIAL RGC TIA
Test chips of the differential RGC TIA were implemented
in a 0.25- m standard CMOS technology with a single poly
and five metal layers. The core area occupies 0.13
ESD protection diodes with parasitic capacitance of 0.7 pF are
integrated in all pads. The TIA chip is then integrated with a
350 m GaAs p-i-n photodiode and a couple of planar
spiral inductors on an oxidized phosphorous-silicon (OPS) sub-
strate by incorporating the MCO technology.
The MCO technique enhances the electrical isolation char-
acteristics between noise-susceptible analog circuits and noisy
0.16 mm .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004973
Fig. 3.Microphotograph of the MCO TIA.
different bit rates: (a) 622 Mb/s; (b) 800 Mb/s; (c) 1 Gb/s; and (d) 1.25 Gb/s.
Measuredoptical eye diagrams ofthe MCOTIA for ? ?? PRBSwith
digital logic, and hence, results in significant reduction of sub-
strate coupling noise . It also provides good thermal conduc-
tivity. Fig. 3 shows the microphotograph of the fabricated MCO
TIA (occupying the area of 5
For optical measurements, a low-cost 850-nm VCSEL diode
and the p-i-n photodiode are utilized as a light source and an
optical detector, respectively.The photodiodeyields the respon-
sivity of 0.6 A/W at 850 nm with parasitic capacitance of 1 pF
and parasitic resistance of 25
optical eye diagrams of the MCO TIA at different data rates
of 622-Mb/s, 800-Mb/s, 1-Gb/s, and 1.25-Gb/s
It is clearly seen that wide eye openings are obtained up to
1-Gb/s operations.The maximum voltage swing is measured to
be 200 m
in a single-ended output. The peak-to-peak jitter
is measured to be less than 176 ps.
Electrical measurements were also conducted to measure the
frequency response of the differential RGC TIA. To facilitate
the measurements, the TIA chip was mounted on an FR-4
PC-board test fixture with the equivalent circuit of a 1-pF
photodiode . Then, the test module was measured in the fre-
quency range of 10 MHz–1 GHz using an HP8753ES network
analyzer with a test power level of
measured data, demonstrating 80-dB
and 670-MHz bandwidth for 1-pF photodiode capacitance. The
5 mm ).
. Fig. 4 shows the measured
15 dBm. Fig. 5 depicts the
Fig. 5.Electrically measured frequency response of the RGC TIA.
Fig. 6.Measuredopticalsensitivity oftheMCOTIA for 1-Gb/s? ??PRBS.
bandwidth shrinks to 360 MHz with no shunt peaking inductor
The equivalent input noise current spectral density of the dif-
ferential RGC TIA is measured by using an HP8650A spectrum
analyzer and a wide-band low-noise amplifier (LNA) in the fre-
quency range of 10 MHz–700 MHz. The average noise current
of 0.54 A is achieved, which corresponds to the sensitivity of
21 dBm for a BER of 10with the extinction ratio of 9 dB.
However, the optical sensitivity of the MCO TIA is measured
17 dBm for 10 BER with 1-Gb/s
shown in Fig. 6. This 4-dB discrepancy may be attributed to the
sensitivity of the wide-band LNA, the coupling loss between
fiber and the p-i-n photodiode, and the unwanted lights from
The digital switching noise effect on the sensitive analog
TIA is also examined. For this purpose, a VCO was integrated
with the differential RGC TIA on both an OPS substrate and a
silicon substrate, because the VCO is one of the main sources
of switching noise and jitter degradation in optical receiver
systems. The VCO was designed as a three-stage self-biased
ring oscillator . Then, the substrate coupling noise effect
was investigated from the output eye diagrams of both TIAs.
974IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004
RGC TIA on (a) MCO OPS substrate and on (b) SoC silicon substrate with
VCO switched on at different data rates of 155 and 622 Mb/s.
Measured digital switching noise effect on the eye diagrams of the
and its measured electrical crosstalk between adjacent channels.
Fig. 7 shows the measured eye diagrams when the VCO is
switched on at different data rates of 155 Mb/s and 622 Mb/s.
It is clearly seen that little degradation of the eye diagrams
is detected in the MCO TIA, whereas the performance of the
high-speed mixed-mode SoC is considerably deteriorated due
to the high conductivity of silicon substrate. These results
confirm that the MCO technology can effectively mitigate the
substrate coupling noise in high-speed mixed-mode circuits.
DC measurements show that the MCO TIA module dissipates
27 mW from a single 2.5-V supply.
Furthermore, a four-channel MCO TIA array was imple-
mented on an OPS substrate for the applications of parallel
optical interconnects. Fig. 8 shows the chip microphotograph
of the array, where each channel incorporates the differential
RGC TIA. Electrical measurements reveal that the MCO TIA
array achieves less than
40-dB crosstalk between adjacent
channels within the bandwidth. The performance of the MCO
TIA is summarized in Table I.
PERFORMANCE SUMMARY OF THE MCO TIA
A 1-Gb/s fully differential RGC TIA has been implemented
in a 0.25- m standard CMOS technology for parallel optical
interconnects. Employing the MCO technology, the TIA chip
is integrated with a p-i-n photodiode and planar inductors on an
of 80 dB , the sensitivity of
the interchannel crosstalk of less than
digital switching noise effect. The MCO TIA module dissipates
27 mW from a single 2.5-V supply.
17 dBm for the BER of 10
40 dB, and negligible
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