IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995251
A 4.4 ns CMOS 54
Using Pass-Transistor Multiplexer
Norio Ohkubo, Makoto Suzuki, Member, IEEE, Toshinobu Shinbo, Toshiaki Yamanaka, Member, IEEE,
Akihiro Shimizu, Katsuro Sasaki, Member, IEEE, and Yoshinobu Nakagome, Member, IEEE
Abstract—A 54 ? ? ? 54-b multiplier using pass-transistor mul-
tiplexers has been fabricated by 0.25 ? ? ?m CMOS technology.
To enhance the speed performance, a new 4-2 compressor and
a carry lookahead adder (CLA), both featuring pass-transistor
multiplexers, have been developed. The new circuits have a speed
advantage over conventional CMOS circuits because the number
of critical-path gate stages is minimized due to the high logic
functionality of pass-transistor multiplexers. The active size of
the 54 ? ? ? 54-b multiplier is 3.77 ? ? ? 3.41 mm. The multiplication
time is 4.4 ns at a 2.5-V power supply.
cessors. In particular, high-speed multiplication is becoming
increasingly important in RISC’s, DSP’s, graphics accelera-
tors, and so on, because of increasing demand for multimedia
applications. Recent high-end microprocessors call for an
operating frequency of 200 MHz or over. Furthermore, a
multiplier will be required for single-clock-cycle operation.
However, no CMOS 54
54-b multiplier with a delay time
less than 5 ns has yet been reported , .
This paper describes a 54
oped formantissa multiplication of 2 double-precision num-
bers, as outlined in the IEEE standard . The target multipli-
cation time is less than 5 ns. To reduce the multiplication
time, a new 4-2 compressor and a carry lookahead adder
(CLA), both featuring pass-transistor multiplexers, have been
developed. The new circuits provide a speed advantage over
conventional CMOS circuits because the number of critical-
path gate stages is minimized due to the high logic func-
tionality of pass-transistor multiplexers. In addition, power
reduction is important in attaining such high performance. For
this purpose, we employed 0.25
reduced the supply voltage to 2.5 V.
The architecture of the 54
in Section II. In Section III, the circuit design based on
Booth’s algorithm, as well as the design of the pass-transistor
NHANCING the performance of floating-point operation
is indispensable for current high-performance micropro-
54-b multiplier macro devel-
m CMOS technology and
54-b multiplier is described
Manuscript received August 1, 1994; revised 10/21/94.
N. Ohkubo, M. Suzuki, T. Yamanaka, and Y. Nakagome are with the Central
Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan.
T. Shinbo and A. Shimizu are with the Hitachi VLSI Engineering Corpo-
ration, Kodaira, Tokyo 187, Japan.
K. Sasaki is with the R&D Division, Hitachi America, Ltd., Brisbane, CA
IEEE Log Number 9408745.
Block diagram of the 54 ? 54-b multiplier usingpass-transistor
multiplexer, 4-2 compressor, and carry lookahead adder are
discussed. Section IV describes the fabrication of a test chip.
Some experimental results are shown in Section V, and the
conclusions are summarized in Section VI.
The block diagram of the 54
in Fig. 1. It employs Booth’s algorithm , Wallace’s tree
, and a conditional carry-selection (CCS) adder . The
number of partial products is halved by Booth’s algorithm.
The partial products are summed by Wallace’s tree, without
carry propagation. The summed results are then added by the
CCS adder with high-speed carry propagation.
Reducing the delay of Wallace’s tree is important in reduc-
ing multiplication time, so we used a 4-2 compressor, which
has 5 inputs and 3 outputs. The carry-out (
the next higher bit 4-2 compressor’s carry-in (
in Fig. 1. Without propagating the carry to a higher bit, the
4-2 compressor can add four partial products (II-I4) because
the carry-out (
) does not depend on the carry-in (
using this 4-2 compressor, only four addition stages are needed
for Wallace’s tree, as shown in Fig. 1. It is known that the
4-2 compressor has a speed advantage over full-adder-based
designs, because of the reduced number of addition stages
, . For further improvement, we have developed a new
4-2 compressor that reduces the critical path gate stages by
exploiting the high logic functionality of the pass-transistor
54-b multiplier is shown
) is connected to
), as shown
0018–9200/95$04.00 1995 IEEE
OHKUBO et al.: A CMOS MULTIPLIER USING PASS-TRANSISTOR MULTIPLEXER257
Toshinobu Shinbo was born in Hokkaido, Japan,
on May 10, 1969. He received the B.S. degree from
Iwate University, Iwate, Japan, in 1992.
In 1992 he joined Hitachi VLSI Engineering
Corporation, Tokyo, Japan, where he has been en-
gaged in research and development of submicrom-
eter CMOS LSI’s.
Toshiaki Yamanaka (M’87) received the B.S. and
M.S. degrees in electrical engineering from the Uni-
versity of Electro-Communications, Tokyo, Japan,
in 1980 and 1982, respectively.
In 1982 he joined the Central Research Labo-
ratory, Hitachi, Ltd., Tokyo, Japan. He has been
engaged in the development of device and process
technologies for high-density CMOS static RAM’s.
His research topic is to develop a polysilicon-TFT
memory cell for 4 M and 16 M SRAM’s. His current
interests also include the development of high-speed
CMOS technology for logic and memory LSI’s.
Akihiro Shimizu was born in Tochigi, Japan, in
1958. He received the B.S. degree in material
physics from the University of Hiroshima, Japan,
He was with Hitachi Microcomputer Engineering,
Ltd., where he worked on MOS device technology
from 1981 to 1984. Since 1985 he has been
with HitachiVLSI Engineering
Tokyo, Japan. His current research interests are
in submicrometer MOS device technology for
SRAM’s and reliability physics, such as hot-carrier
Mr. Shimizu is a member of the Japan Society of Applied Physics and the
Institute of Electronics, Information, and Communication Engineers of Japan.
Katsuro Sasaki (M’88) received the B.S. degree in
electrical engineering and the M.S. degree in elec-
tronic engineering from the University of Tokyo,
Japan, in 1976 and 1978, respectively.
In 1978 he joined the Semiconductor Division,
Hitachi, Ltd., Tokyo, Japan, where he was involved
in the development of a 16-kbit low-power CMOS
static RAM and 16-kbit, 64-kbit, and 1-Mbit high-
speed CMOS static RAM’s. From 1985 to 1986
he worked on the research of polysilicon TFT’s at
Massachusetts Institute of Technology, Cambridge.
In 1978 he joined the Central Research Laboratory, Hitachi, Ltd., Tokyo,
Japan, where he worked on high-speed circuits and devices for submicrometer
4-, 16-, and 64-Mbit static RAM’s. He was also in charge of the research and
development of CMOS/BiCMOS circuits for high-speed logic LSI’s from
1991 to 1993 as Manager of a high-speed circuit research group. Since March
1993 he has been in charge of the research and development of DSP’s and
DSP-related software as Manager of the Semiconductor Research Laboratory,
Research and Development Division, Hitachi America, Ltd., Brisbane, CA.
Mr. Sasaki is a member of the Institute of Electronics, Information, and
Communication Engineers of Japan.
Yoshinobu Nakagome (M’86) was born in Tokyo,
Japan, on February 21, 1956. He received the B.S.
degree in electrical and electronic engineering and
the M.S. degree in applied electronics from Tokyo
Institute of Technology, Japan, in 1978 and 1980,
In 1980 he joined the Central Research Labo-
ratory, Hitachi, Ltd., Tokyo, Japan, where he was
engaged in research on MOS device physics and
technologies. Since 1983 he has been working on
high-density MOS dynamic memories. He has also
been in charge of the research and development of CMOS circuits for high-
speed logic LSI’s since 1993. He was a Visiting Industrial Fellow at the
University of California, Berkeley, from 1987 to 1988.
Mr. Nakagome is a member of the Institute of Electronics, Information,
and Communication Engineers of Japan.