Article

# A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

Central Res. Lab., Hitachi Ltd., Tokyo

IEEE Journal of Solid-State Circuits (Impact Factor: 3.06). 04/1995; DOI: 10.1109/4.364439 Source: IEEE Xplore

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**ABSTRACT:**This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of the smallest multiplier-cells, the 4 bit multiplier. Synthesized results could reach as high as 425.53MHz using SMIC 0.13um CMOS technology library under the worst case condition.Electronics, Communications and Control (ICECC), 2011 International Conference on; 01/2011 - [Show abstract] [Hide abstract]

**ABSTRACT:**This paper presents a new pipeline architecture for low-power and high-speed digital adaptive equalizer. The proposed architecture achieves enhancement in terms of speed and power consumption by sharing the input delay stage with input data multiplication and by scaling down the supply voltage. The adaptive equalizer for PRML disk-drive read channels adopting the proposed pipeline architecture is designed and fabricated with the 0.6 m CMOS single poly triple metal process technology. The adaptive equalizer employing proposed pipeline architecture occupies 3.2 mm × 2.2 mm, achieves maximum operating frequency of 200 MHz, and dissipates 1.22 mW/MHz at 3.3 V supply voltage. Experimental results show 16% enhancement in speed and 23% less power dissipation.Analog Integrated Circuits and Signal Processing 01/2003; 34(3). · 0.55 Impact Factor -
##### Conference Paper: A novel high-speed low-power binary signed-digit adder

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**ABSTRACT:**Addition is one of the most important arithmetic operations in digital computation. Optimization of adders' speed, power, and area is a challenging task. To this end, redundant number system has been proposed in the literatures. In this paper, we propose a new redundant binary signed-digit adder that not only utilizes specific encoding for the input operands, but also uses a new efficient adder structure. Using this technique we can generate low power signed digit adders that perform fast additions. The comparisons show delay, power and area reduction both on FPGA and Synopsys Design Vision tool.Computer Architecture and Digital Systems (CADS), 2012 16th CSI International Symposium on; 01/2012

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