A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

Central Res. Lab., Hitachi Ltd., Tokyo
IEEE Journal of Solid-State Circuits (Impact Factor: 3.06). 04/1995; DOI: 10.1109/4.364439
Source: IEEE Xplore

ABSTRACT A 54×54-b multiplier using pass-transistor multiplexers has
been fabricated by 0.25 μm CMOS technology. To enhance the speed
performance, a new 4-2 compressor and a carry lookahead adder (CLA),
both featuring pass-transistor multiplexers, have been developed. The
new circuits have a speed advantage over conventional CMOS circuits
because the number of critical-path gate stages is minimized due to the
high logic functionality of pass-transistor multiplexers. The active
size of the 54×54-b multiplier is 3.77×3.41 mm. The
multiplication time is 4.4 ns at a 3.5-V power supply

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