A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer

Central Res. Lab., Hitachi Ltd., Tokyo
IEEE Journal of Solid-State Circuits (Impact Factor: 3.11). 04/1995; 30(3):251 - 257. DOI: 10.1109/4.364439
Source: IEEE Xplore

ABSTRACT A 54×54-b multiplier using pass-transistor multiplexers has
been fabricated by 0.25 μm CMOS technology. To enhance the speed
performance, a new 4-2 compressor and a carry lookahead adder (CLA),
both featuring pass-transistor multiplexers, have been developed. The
new circuits have a speed advantage over conventional CMOS circuits
because the number of critical-path gate stages is minimized due to the
high logic functionality of pass-transistor multiplexers. The active
size of the 54×54-b multiplier is 3.77×3.41 mm. The
multiplication time is 4.4 ns at a 3.5-V power supply

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    • "Figure 11(a) shows one of the CTD-based representations for constanttime BCS addition. Figures 11(b), (c) and (d) show the binary logic implementations reported in [15]–[17] "
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    ABSTRACT: This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with multiple-valued logic devices, while a low-level CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.
    IEICE Transactions on Electronics 11/2006; E89C(11). DOI:10.1093/ietele/e89-c.11.1645 · 0.39 Impact Factor
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    • "Proposed Transistors in Encoder 30 26 20 18 MUXs in Selector -3 2 3 2 Critical Path (gate) 6 5 3 3 Delay (ns) 1.06 0.71 0.68 0.64 TABLE 3 COMPARISON OF MULTIPLIER Ohkubo[2] "
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    ABSTRACT: In this paper, we describe a 64×64-bit high performance multiplier based on multiplexer cells which is implemented with pass transistor logic. A multiplexer-select Booth encoders was developed to increase speed and reduce the hardware cost. Moreover, a partitioned method was introduced in the design to save the propagate time of final adder. Realistic simulation using extracted timing parameters from the layout shows that the propagation time of the critical path is 2.82ns at 1.8V on 0.18μm CMOS technology.
    The 6th International Conference On ASIC, 2005 (ASICON 2005), Shanghai, China; 11/2005
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    • "The partial product generator is designed using three 2-1 multiplexers. In this circuit the critical path includes only two 2-1 multiplexer, while previously designed partial product generators are using three 2-1 multiplexers [1] or XOR gate and actually 4 primitive gates [2] in their critical paths. Because of the large number of partial product generators used in the multiplier circuit, simplicity of this circuit leads to a lower area and power consumption. "
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    ABSTRACT: In this paper, we present a high-speed low power signed multiplier with improved booth encoders and partial product generators. Our partial product generator includes only two 2-1 multiplexers in it's critical path, while previously-designed partial product generators are using three multiplexers [1] or equivalently more logic level gates [2] in their critical paths. 4:2 Compressors connected in a Wallace tree are used for adding partial products. To reduce area and improve the speed, a distributed adder is used. After the multiplier structure designed, the best logic style for this application was selected based on comparisons made by HSPICE simulations. Then, transistor sizes were optimized to obtain a high speed, low power, and area efficient multiplier in a 0.5m CMOS process.


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