Design of capacitorless LDO with compensation circuits.

Abstract

This project proposes two solutions to the present bulky external capacitor low-dropout voltage regulators (LDO). The large output capacitor is reduced allowing for greater power system integration for system-on-chip (SoC) application, while the LDO system still maintains good stability by inserting the compensation circuit block. The capacitorless LDOs were fabricated in a commercial 0.18um CMOS technology with 100mA full load and 3V power supply. The two designed LDO systems are capable of regulating a 2.8V output voltage with output load of 50pF and 0pF respectively. The first proposed compensation circuit block makes use of a current amplifier. In this LDO proposal, the output voltage spike is reduced to as low as 200mV in a full load transient, the response time is shortened and the phase margin is optimized to 88.8 in the transient response. The second proposed compensation circuit block uses a buffer stage and a miller capacitor. The second LDO proposal has a 400mV voltage spike in a full load transient, and its phase margin is 65.6. The simulation results are obtained from the Cadence ADE Environment, only the typical model is measured. The layout of the first LDO is 0.1265 (0.557mm0.227mm).