Article

Efficient Output Waveform Evaluation of a CMOS Inverter Based on Short-Curcuit Current Prediction

12/2002;
Source: OAI

ABSTRACT SUMMARY A novel approach for obtaining the output waveform, the propagation delay and the short-circuit power dissipation of a CMOS inverter is introduced. The output voltage is calculated by solving the circuit dierential equation only for the conducting transistor while the eect of the short-circuit current is con- sidered as an additional charge, which has to be discharged through the conducting transistor causing a shift to the output waveform. The short-circuit current as well as the corresponding discharging current are accurately predicted as functions of the required time shift of the output waveform. A program has been developed that implements the proposed method and the results prove that a signicant speed im- provement can be gained with a minor penalty in accuracy. Copyright ? 2002 John Wiley & Sons, Ltd.

0 Bookmarks
 · 
121 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The paper discuss the design of 1-bit full adder circuit using Shannon theorem. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring and Restoring divider circuits. The proposed adder and divider schematics are designed by using DSCH2 CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The divider circuits are designed by using standard CMOS 0.35 microm feature size and corresponding power supply 3.5 V. The parameters analyses are carried out by BSIM 4 analysis. We have compared the simulated results of the Shannon based divider circuit with CPL and CMOS adder cell based divider circuits. We have further compared the results with published results and observed that the proposed adder cell based divider circuit dissipates lower power, gives faster response, lower latency, low EPI and high throughput.
    Recent patents on nanotechnology. 02/2009; 3(1):61-72.
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper describes an analytical delay model for transistor sizing. Two primitives are selected to be mapped for computing gate delay. These primitives model the short-channel effect and body effect in deep submicron CMOS circuits. A mapping algorithm for arbitrary serial-parallel structures is adopted. The delay of complex gates using such mappings to primitives is found to be within 10% of SPICE for most of the gates. The delay model is incorporated into a transistor sizing algorithm based on TILOS. Also presented are the experimental results for several circuits from LGSynth91 benchmark suite.
    Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific; 02/2005
  • [Show abstract] [Hide abstract]
    ABSTRACT: Gaussian pulse is widely used in communication systems. The true Gaussian function is not physically realizable, but it can be approximated through linear functions. This paper presents a Gaussian pulse approximation approach to generate a quasi-Gaussian pulse by using the transient response of a CMOS inverter. The basic structure of the proposed design includes a digital variable square pulse generator, a Gaussian pulse generator and a small antenna model. The digital variable square pulse generator makes the amplitude and width of the generated quasi-Gaussian pulse tunable. The proposed pulse generator works well for three different electrical small antenna models. The simulation results show that the generated pulse approximates the Gaussian shape very well and the radiated signal at the antennas is compliant with the Federal Communication Commission's spectral mask for the 0–960 MHz band. The simple structure of this Gaussian pulse generator lends itself to a low-power, single-chip UWB transceiver solution. Copyright © 2008 John Wiley & Sons, Ltd.
    International Journal of Circuit Theory and Applications 11/2008; 38(4):383 - 407. · 1.29 Impact Factor

Full-text

View
3 Downloads
Available from