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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. Theor. Appl. 2002; 30:547–566 (DOI: 10.1002/cta.207)

E?cient output waveform evaluation of a CMOS inverter based

on short-circuit current prediction

A. Chatzigeorgiou1;∗;†and S. Nikolaidis2;‡

1Department of Applied Informatics; University of Macedonia; 54006 Thessaloniki; Greece

2Department of Physics; Aristotle University of Thessaloniki; 54006 Thessaloniki; Greece

SUMMARY

A novel approach for obtaining the output waveform, the propagation delay and the short-circuit power

dissipation of a CMOS inverter is introduced. The output voltage is calculated by solving the circuit

di?erential equation only for the conducting transistor while the e?ect of the short-circuit current is con-

sidered as an additional charge, which has to be discharged through the conducting transistor causing a

shift to the output waveform. The short-circuit current as well as the corresponding discharging current

are accurately predicted as functions of the required time shift of the output waveform. A program has

been developed that implements the proposed method and the results prove that a signi?cant speed im-

provement can be gained with a minor penalty in accuracy. Copyright ? 2002 John Wiley & Sons, Ltd.

KEY WORDS: propagation delay; short-circuit power; CMOS inverter; timing analysis

1. INTRODUCTION

The development of digital integrated circuits with short design cycles requires accurate and

fast timing and power simulation. Unfortunately, simulators which employ numerical methods,

such as SPICE are prohibitively slow for large designs. The need for analytical methods

which can produce accurate results at short times is obvious and extended research has been

conducted for the CMOS inverter [1–10] which forms a basic block to which all CMOS

structures can be diminished. Since complex CMOS gates can be reduced to an equivalent

inverter that has the same performance [11,12] it is su?cient to seek accurate and e?cient

models for the transient analysis of the inverter. Another important reason for focusing on the

CMOS inverter is its extensive use in clock distribution networks and buses in most integrated

circuits and the corresponding power that is consumed on these inverters [13].

Analytical modelling techniques at the inverter level are very accurate but this comes at

the cost of increased complexity. The analysis of the inverter is complicated mainly due to

∗Correspondence to: Dr. A. Chatzigeorgiou, Department of Applied Informatics, University of Macedonia, 156

Egnatia, St., 54006 Thessaloniki, Greece.

†E-mail: alec@ieee.org

‡E-mail: snikolaid@physics.auth.gr

Received 29 November 2001

Revised 1 March 2002

Copyright ? 2002 John Wiley & Sons, Ltd.

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A. CHATZIGEORGIOU AND S. NIKOLAIDIS

the presence of the short-circuit current which acts parasitically on the output evolution. The

di?erential equation which describes the operation of the circuit has to be solved taking into

account the current of both the pMOS and the nMOS transistor. This leads to complicated

expressions for the output waveform increasing signi?cantly the execution time.

Analytical techniques for the modelling of the CMOS inverter aim at obtaining an output

waveform expression for a ramp input, for each region of operation which is determined by

the mode of operation of each transistor and the status of the input. Several methodologies

have been developed which can be categorized according to the transistor current model used

(Shichman–Hodges square law [1], nth power law [2], alpha power law [3,4], bulk charge

square law [5]) and according to the parameters and second-order e?ects which have or

have not been taken into account (negligible short-circuit current in Reference [1], input-to-

output coupling capacitance [6] and carrier velocity saturation e?ects [4]). An integration of

all e?ects into one method has been presented in References [3,8]. A common drawback of

all these techniques is that they result in complicated expressions for the output waveform

thus requiring increased computational power and execution time in case of a simulator.

Macromodelling techniques for the calculation of the delay and short-circuit power dissipation

of CMOS structures have been presented in References [9,10], respectively, where parameters

such as input transition time, input-to-output coupling and second-order e?ects of submicron

transistors are incorporated in closed form macromodels.

In this paper a method which takes into account all of the above-mentioned parameters

and second-order e?ects avoiding however the intricacy of the short-circuit current by solving

the di?erential equation that describes the circuit operation considering only the conducting

transistor is introduced. The e?ect of the short-circuit current is taken into account as an

additional charge which has to be discharged through the conducting transistor. This charge

causes a shift on the output waveform that has been obtained considering only the conducting

transistor. The ‘translation’ of the e?ect of the short-circuit current to a time delay has also

been discussed in a simpli?ed manner in Reference [6] in order to calculate the propagation

delay. However, the charge supplied by the short-circuiting transistor is calculated using ?tting

methods on SPICE simulation results resulting in a semi-empirical method, which is inaccurate

for submicron technologies. In the approach proposed in References [7,13] the short-circuit

current has been treated as an additional charge which however was calculated on an initial

estimate of the output waveform, thereby resulting in large errors.

The method for the evaluation of the output response by shifting the initially obtained

waveform is described in Section 2 while in Section 3 the proposed method is extended in

order to calculate the short-circuit energy dissipation of an inverter for a single transition.

Results of the proposed method in terms of accuracy and execution time and comparisons

with SPICE and other approaches are given in Section 4. Finally, we conclude in Section 5.

2. OUTPUT WAVEFORM EVALUATION

Let us consider the inverter of Figure 1(a) whose operation is described for a rising input

ramp with transition time ? by the following di?erential equation:

CLdVout

dt

=iCM+ ip− in

(1)

Copyright ? 2002 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2002; 30:547–566

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EVALUATION OF A CMOS INVERTER

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Figure 1. (a) Actual inverter, (b) conducting transistor.

where

iCM=CM

?dVin

dt

−dVout

dt

?

is the current through the coupling capacitance CM between input and output [3,14]. The

case of a falling input ramp is symmetrical. If the short-circuit current ipis neglected (Figure

1(b)), then the output waveform can be obtained by solving the above equation according to

the regions of operation of the conducting nMOS transistor. This waveform will be referred

to as initial waveform, Voutinit(t). For submicron devices the output waveform is obtained with

excellent accuracy using the alpha-power law model for the transistor currents (here presented

for an nMOS transistor) [4]:

where VDSATis the drain saturation voltage, kl;ksare the transconductance parameters, ? is the

carrier velocity saturation index and VTNis the threshold voltage. It should be mentioned that

in the solution of the di?erential equation for the single transistor, the coupling capacitance CM

should also take into account the pMOS transistor gate-to-drain capacitance. The expressions

for Voutinit(t) are given in Appendix A.

Calculating the output waveform considering only the conducting current leads not only to

simpler expressions for the output waveform and thus to shorter execution time but is also

substantially more simple in terms of program complexity. In Figure 2 the decision diagrams

and the operating regions through which the output evolves for the fully analytical method

[3] where both transistors are considered and for the proposed method are shown. Each

ID=

0VGS6VTN: cuto? region

kl(VGS− VTN)a=2VDS

ks(VGS− VTN)a

VDS¡VDSAT: linear region

VDS¿VDSAT: saturation region

(2)

Copyright ? 2002 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2002; 30:547–566

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A. CHATZIGEORGIOU AND S. NIKOLAIDIS

Region 1

nMOS cutoff

pMOS linear

input in transition

Region 2

nMOS saturation

pMOS linear

input in transition

Region 3

nMOS saturation

pMOS saturation

input in transition

Region 4

nMOS saturation

pMOS cutoff

input in transition

Region 4

nMOS saturation

pMOS cutoff

input in transition

t>tn

t>tp

t>tp

t>tsp

Region 5B

Region 6

nMOS linear

pMOS cutoff

input in transition

nMOS linear

pMOS cutoff

input DC

t>tsn

t>τ

Region 5A

nMOS saturation

pMOS cutoff

input DC

Region 6

nMOS linear

pMOS cutoff

input DC

t>tsn

t>τ

t>tsn

t>τ

Region 5C

nMOS linear

pMOS saturation

input in transition

t>tp

Region 1

nMOS cutoff

input in transition

Region 2A

nMOS saturation

input in transition

Region 3A

nMOS linear

input in transition

Region 2B

nMOS saturatio n

input DC

Region 3B

nMOS linear

input DC

t>tn

t>τ

t>τ

t>tsn

t>tsn

Figure 2. Decision diagrams for (a) fully analytical and (b) proposed method.

block represents a region of operation according to the mode of operation of the conducting

and short-circuiting transistor (for the case of an inverter) and the status of the input. On

each edge the condition which must be ful?lled in order for the corresponding transition

from one operating region to another to take place is shown. A program for the simulation

of each structure, inverter or single transistor, should be able to distinguish between the

operating regions by branching according to the speci?ed conditions. Obviously, the output

voltage value at the region boundaries should be calculated for the transient simulation of each

structure.

Timing analysis of a CMOS inverter can be performed either by calculating the output

voltage at each time step thus obtaining the full output waveform or by simply calculating

the propagation delay and the slope of the output at the half-VDD point in order to de?ne an

equivalent ramp for the output waveform, that can be fed as input to the next stage [1]. The

contribution of the program complexity in terms of region boundaries and branching between

them on the total execution time is more intense when only the propagation delay is calculated

rather than the full output waveform.

The discharging of the output when the short-circuit current is neglected is faster than in the

actual inverter since the short-circuit current reduces the e?ective discharging current slowing

down the output evolution. The e?ect of the pMOS short-circuit current can be considered as

an additional charge, Qad, at the output load causing an additional delay, tad, to the output

evolution. This proposition is based on the fact that the slope variation at the half-VDD point

between the output waveform of a single transistor driving an output load and that of an

inverter driving the same load is very small, and thus it can be considered for modelling

purposes that the output waveform is shifted. In Figure 3 the slope of the output waveform

of an inverter at the half-VDD point over the nominal slope, which is the slope of the output

considering only the conducting transistor is displayed for two load capacitance values. As it

can be observed, this ratio remains close to unity, validating the proposed approach.

The delay tad is calculated as the time required to discharge Qad through the conducting

nMOS device.

Copyright ? 2002 John Wiley & Sons, Ltd.Int. J. Circ. Theor. Appl. 2002; 30:547–566

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EVALUATION OF A CMOS INVERTER

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0.0 1.0 2.03.04.0 5.0

Input transition time (ns)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

actual slope / nominal slope

0.35 um

CL = 100 fF

CL = 50 fF

Figure 3. Slope variation between single transistor and inverter at VDD=2 (HP 0:35 ?m,

Wn=1:4 ?m, Wp=2:1 ?m, VDD=3:3 V).

Consequently, the actual output waveform can be approximated by shifting the initial wave-

form by tad:

Vout(t)=Voutinit(t − tad) (3)

However, the problem is that if the short-circuit current is calculated on the initial waveform,

the charge would be overestimated while the corresponding nMOS discharging current, Idch,

would be underestimated leading to an overestimated additional delay, tad0(Figure 4). That

is because the initial waveform evolves faster than that of the actual inverter resulting in a

larger VDSvalue for the pMOS transistor and a smaller VDSvalue for the nMOS transistor at

each time point. To overcome this problem the proposed technique is employed: The pMOS

short-circuit current and the corresponding discharging nMOS current are calculated on Vout

and therefore result as functions of the additional delay. Thus, tad, can be obtained by solving

tad=Qad(tad)

Idch(tad)

(4)

Consequently, the key point in the proposed approach is the accurate approximation of the

pMOS and nMOS transistor currents as simpli?ed functions of the additional delay, tad.

The actual pMOS short-circuit current can be approximated by a piece-wise linear function

of time [2,15] (Figures 5 and 6). The charge that it contributes can be easily calculated as

Copyright ? 2002 John Wiley & Sons, Ltd.Int. J. Circ. Theor. Appl. 2002; 30:547–566