An MC-SS Platform for Short-Range Communications in the Personal Network Context
ABSTRACT Wireless personal area networks (WPANs) have gained interest in the last few years, and several air interfaces have been proposed to cover WPAN applications. A multicarrier spread spectrum (MC-SS) air interface specified to achieve 130Ã¢Â€Â‰Mbps in typical WPAN channels is presented in this paper. It operates in the 5.2Ã¢Â€Â‰GHz ISM band and achieves a spectral efficiency of 3.25Ã¢Â€Â‰bÃ‚Â·sÃ¢ÂˆÂ’1Ã‚Â·HzÃ¢ÂˆÂ’1. Besides the robustness of the MC-SS approach, this air interface yields to reasonable implementation complexity. This paper focuses on the hardware design and prototype of this MC-SS air interface. The prototype includes RF, baseband, and IEEE802.15.3 compliant medium access control (MAC) features. Implementation aspects are carefully analyzed for each part of the prototype, and key hardware design issues and solutions are presented. Hardware complexity and implementation loss are compared to theoretical expectations, as well as flexibility is discussed. Measurement results are provided for a real condition of operations.
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ABSTRACT: Opportunistic radio (OR) systems usually identify and exploit unused spectrum resources in the frequency domain. Targeting opportunities in the time domain of course yields more stringent timing requirements for the opportunistic system, but enables a more optimized resource usage when spectrum opportunities are limited, like for unlicensed bands. This paper describes a hardware demonstrator of such an OR system detecting and using temporal opportunities, and particularly focuses on the key modules required to achieve the opportunistic functionality. To this end, it presents an exclusive implementation of a cyclostationarity sensing algorithm, and proposes a low complexity decision-making algorithm, which performs real-time regulation of the OR communications. Finally, it includes collaborative sensing features to address efficiently the hiddennode scenario. The demonstrator operates in the 2.4 GHz band, and has been validated by sharing the spectrum resource with a standard IEEE 802.11g primary system (PS) running a video streaming application, without perceptible impact of the OR system. It should finally be emphasized that the concepts and techniques undertaken can easily be transposed to any packet based transmission over OFDM or W-CDMA PHY.Cognitive Radio Oriented Wireless Networks and Communications, 2009. CROWNCOM '09. 4th International Conference on; 07/2009
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ABSTRACT: This paper presents a generic hardware-MAC for systems de- signed based on high rate (IEEE 802.15.3) and low rate (IEEE 802.15.4) Wireless Personal Area Networks. Functionality that are better run in hardware are moved over from the software part of the MAC layer. An easy to access memory like inter- face has been defined for data and control transfer between the software and hardware parts of the MAC layer. A key challenge in designing such a system was to arrive at a generic architec- ture without compromising with either of the standards on the lines of which the two systems are implemented. Emphasis on reuse of the modules has been done in order to avoid repeti- tion of design and implementation effort and in turn reducing the time required for testing. The design has been successfully tested on different FPGA platforms.01/2008;
Hindawi Publishing Corporation
EURASIP Journal on Wireless Communications and Networking
Volume 2008, Article ID 830273, 12 pages
An MC-SS Platform for Short-Range Communications in
the Personal Network Context
Dominique Noguet,1Marc Laugeois,1Xavier Popon,1B. Balamuralidhar,2Manuel Lobeira,3
Narasimha Sortur,2Deepak Dasalukunte,4Cedric Dehos,1and Zeta Bakirtzoglou5
1Leti Minatec Center (CEA), 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
2Tata Consultancy Services Limited (TCS Limited company), 96 Epip-ip Industrial Area, Whitefield Road 560066, Bangalore, India
3ACORDE S.A., Centro de Desarrollo Tecnol´ ogico, Avenida de los Castros S/N, 39005 Santander, Cantabria, Spain
4Department of Electrical and Information Technology, Lund University, P.O. Box 118, 22100 Lund, Sweden
5Intracom S.A. Telecom Solutions, 19.7 km Markopoulou Ave, 19002 Peania Attika, Greece
Correspondence should be addressed to Dominique Noguet, firstname.lastname@example.org
Received 4 June 2007; Revised 8 September 2007; Accepted 16 December 2007
Recommended by Luc Vandendorpe
Wireless personal area networks (WPANs) have gained interest in the last few years, and several air interfaces have been proposed
channels is presented in this paper. It operates in the 5.2GHz ISM band and achieves a spectral efficiency of 3.25b · s−1· Hz−1.
Besides the robustness of the MC-SS approach, this air interface yields to reasonable implementation complexity. This paper
focuses on the hardware design and prototype of this MC-SS air interface. The prototype includes RF, baseband, and IEEE802.15.3
compliant medium access control (MAC) features. Implementation aspects are carefully analyzed for each part of the prototype,
and key hardware design issues and solutions are presented. Hardware complexity and implementation loss are compared to
theoretical expectations, as well as flexibility is discussed. Measurement results are provided for a real condition of operations.
Copyright © 2008 Dominique Noguet et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly
Personal Networks (PNs) are a recent paradigm that en-
able an individual to experience connectivity with his de-
vices with unrestricted geographic span . This network
concept is leveraged by the availability of reliable wireless
links between the devices in the user vicinity. The analysis of
user’s needs carried out in  has shown two typical classes
of applications that can be differentiated by the data rate
range; they require low data rate (LDR), lower than 250kbps
and high data rate (HDR), up to 100Mbps. Other studies
specifically its dynamicity [3, 4], a specific attention must be
taken in the design of the physical layer (PHY) of these inter-
faces. New air interfaces have been specified for short-range,
very high data rate applications, under the framework of the
IEEE802.15.3 standard. However, a consensus could not be
reached on a single solution among the systems that were
proposed. One of the most famous systems is probably Wi-
Media which targets 480Mbps using multiband orthogonal
frequency-division multiplexing (OFDM) . New trends
in regulation (e.g., ) indicate that the future worldwide
band for ultra-wideband operation will move to higher fre-
quency though leading to more power consuming and costly
implementation. Besides, most of the applications foreseen
require either lower data rate or far higher like wireless high-
definition multimedia interface (HDMI).
The air interface presented in this paper targets applica-
tions up to 130Mbps at reasonable implementation cost and
power consumption. It is a mixture of multicarrier OFDM-
based technique together with spreading which was initially
proposed in . This approach provides many degrees of
diversity over the intrinsic advantages of OFDM systems,
namely, a potentially low-complexity equalizer and robust-
ness against frequency-selective channels (e.g., ) that is
strengthened by code spreading. The use of time division
multiplex access (TDMA) prevents the system from classical
intercode interference experienced in code division multiple
2EURASIP Journal on Wireless Communications and Networking
Figure 1: PHY functional block diagram.
MAC & PHY
Figure 2: PHY frame format.
access (CDMA) approaches when many asynchronous users
are sharing the same band. Moreover, this air interface ex-
hibits a very high degree of flexibility from which link adap-
tation techniques can benefit .
This paper focuses on the design of a hardware platform
for up to 130Mbps operating in the 5.2GHz ISM band. Its
A real-time implementation of the PHY layer runs on an
FPGA and a wideband radio front-end providing over the air
interface. The paper is divided into 6 sections. In Section 2, a
short description of the air interface and the related param-
eters is given. In Section 3, some aspects of the MAC pro-
tocol and its implementation are detailed. In Section 4, the
baseband processing hardware design is described and com-
plexity issues are discussed. In Section 5, the radio front-end
selection is discussed. In Section 6, the global hardware ar-
chitecture and platform are described. Finally, Section 7 pro-
vides measurement results obtained with the prototype.
2. OVERVIEW OF THE SELECTED MC-SS SYSTEM
The MC-SS air interface detailed in this paper, referred to as
the MAGNET HDR (M-HDR), has been optimized for wire-
less personal area networks (WPANs) in the PN context. Un-
like cellular and wireless LAN systems, peer-to-peer commu-
nication (especially from data traffic point of view) will hap-
pen in such a context. In this case, simultaneous communi-
cation between different users will yield to high interference
for which CDMA would require high complexity multiuser
detectors, which is not compliant with the low complex-
ity requirement of the M-HDR system. Therefore, a TDMA
scheme was chosen. This scheme also has the advantage of
being compliant with the IEEE802.15.3 standard. Regarding
the PHY, the M-HDR air interface is based on multicarrier
for WPAN environment. An overview of the baseband PHY
operations is illustrated by the block diagram of Figure 1.
The M-HDR is based on a coded OFDM modulation us-
ing convolutional coder. The data are spread over the sub-
carriers by the spreading and multicode blocks. This func-
tion aims at a better exploitation of channel diversity, thus
yields to more robustness . Preamble information is then
appended in the time domain to build the PHY frame struc-
ture described in Figure 2.
At the input of the receiver, automatic gain control
(AGC) and time/frequency synchronization are performed
in the time domain. The synchronization block, which is
critical in OFDM systems, is detailed in Section 4. After
the OFDM demodulation, the channel is estimated using a
least square estimator over full pilot symbols. This is based
on the assumption of low device velocity in WPAN con-
text. After the despreading, the bits are demapped from
the QPSK, 16-QAM, or 64-QAM, according to the mode
selected. The range of data rate envisaged is from few of
Mbps to 130Mbps, which corresponds to HDR-WPAN sce-
narios identified in the MAGNET project . Two modes
of operations using 20MHz and 40MHz bandwidth han-
dling up to 65 and 130Mbps, respectively, are considered
for additional flexibility. The maximal spectral efficiency of
3.5bits · s−1· Hz−1is achieved using the 64-QAM. Detailed
rationale for parameters is given in Table 1, choices can be
found in [7, 10].
The generic MAC architecture for a device capable of sup-
porting M-HDR air interface has been developed with the
functional partitioning between the host and the network
interface card (NIC). The NIC implements the M-HDR air
interface prototype which consists of MAC and PHY lay-
ers with an appropriate interface to the host platform. USB
is chosen as the default physical interface to the host. The
network layer and the applications are implemented on the
host platform (Nokia 770 PDA). Figure 3 depicts a high-level
MAC architecture for the M-HDR air interface.
Dominique Noguet et al.3
Table 1: MC-SS air interface main parameters.
Subcarriers for guard band
Subcarriers for pilot
Subcarriers for data
Percentage of guard band
Occupied signal bandwidth
Number of time samples per data symbol
Samples for guard interval
Samples for total OFDM burst
Maximum delay spread
Sample duration in time
Length of data interval in time
Length of guard interval in time
Length of total OFDM interval in time
Percentage of guard interval
Maximum doppler spread
Coherence time = 9/(16π fD)
G1 = 133, G2 = 171
Host (Nokia 770)
Figure 3: M-HDR MAC implementation architecture.
From the implementation point of view, the following
three modules were implemented.
(1) The M-HDR MAC module contains the implemen-
tation for the core MAC functionalities, for example,
beacon transmission for piconet formation, channel
scanning for piconet discovery, synchronization with
other devices, association/disassociation requests to
join and leave piconet, and asynchronous/isochronous
data transmission. On the data path, this module ex-
changes logical link control (LLC) frames with the
host while the control path is used to exchange vari-
ous management commands, for example, set or fetch
configuration parameters. In order to achieve the re-
quired real-time performance, the MAC is partitioned
into hardware (HW-MAC) and software (SW-MAC).
The time-critical and compute-intensive blocks like
CRC generation and ciphering are implemented in
hardware as part of HW-MAC. In the following sub-
sections, we elaborate on both the software and hard-
ware parts of the MAC implementation.
(2) The target module of Figure 3 acts as an interpreter for
the messages it receives from the host over the USB
link. It translates these commands into IEEE-802.15.3
format and forwards them to the M-HDR MAC mod-
ule for further processing.
(3) The host interface module implements the application
programmable interfaces (APIs) which are used by the
higher layers to access various MAC functionalities.
a frame format has been specified. As shown in Figure 4, it
contains a frame identifier field which uniquely identifies the
type oftheframe,a payload sizefieldof twobyteswhichpro-
vides the length of the attached payload. The payload field
consists of the parameters specified with the commands and
can be a maximum of 2048bytes.
4EURASIP Journal on Wireless Communications and Networking
Frame identifierPayload size
Figure 4: Frame format for message exchange between the host and HDR NIC.
CAP, CTA queues
Baseband TX Baseband RX handler
Figure 5: Architecture of the IEEE802.15.3 MAC.
As mentioned above, the implementation of the M-HDR
MAC conforms to the IEEE802.15.3 standard and consists of
the four main building blocks (see Figure 5).
Non-real-time critical features of the MAC are implemented
on a software (SW-MAC) running on an embedded general
purpose processor (GPP).
The TX-frame processing block is mainly responsible for
the formation of the data and command frames to be trans-
mitted. Upon receiving the data/command request from the
frame convergence sublayer (FCSL) or the device manage-
ment entity (DME), the transmitter chain validates the re-
quest, for example, the sourceid, dstid, data length, and
stream index parameters. The MAC frame prepared by at-
taching the MAC header and the payload is then sent to the
transmitter for the transmission over the air.
The transmitter block puts these frames into appropri-
ate device driver queues for transmission. The device driver
implements two transmission queues: one for transmissions
during the contention access period (CAP) and the other for
transmissions during the allocated channel time (CTA).
The RX-frame processing module is responsible for re-
ceiving the frames from the baseband and forwarding them
to the FCSL or DME. The receiver upon receiving the frame
from the baseband verifies the frame for the command or the
data. The command frames are forwarded to the DME block
and the data frames are passed to the FCSL block.
The receiver block coordinates the packet reception be-
tween the receiver chain and the baseband device driver.
From an implementation point of view, each of these
blocks is implemented as a separate thread. These threads
communicate with each other using the Linux message
queues as the interprocess communication (IPC) mecha-
nism. The synchronization between the threads is achieved
Dominique Noguet et al.5
FCSLTX framesRX frames
Figure 6: A multithreaded implementation.
by the use of semaphores. The Linux system calls are imple-
mented as a thin operating system abstraction layer (OSAL).
The OSAL implements the generic wrapper functions over
the OS-dependent system calls.
As shown in Figure 6, the M-HDR MAC module is im-
plemented as a multithreaded program. The module is ac-
tivated by a call to the main function which in turn in-
vokes the initMAC() function. The initMac() function ini-
tializes the framework by creating the threads for each of the
DME, FCSL, transmitter chain, receiver chain, as well as the
transmitter and the receiver blocks. The associated message
queues, registers, memory pool, and PIB (PAN Information
Base) parameters are also initialized.
The hardware MAC (HW-MAC) is present at the interface
between the PHY layer and the SW-MAC layer. It inher-
its some terminal functions of the MAC layer to achieve
improved real-time performance as compared to that per-
formed whenin software.The HW-MAC handlesallthedata
processing in order to provide the PHY layer with the re-
quired format of the packet to be transmitted . Similarly, the
HW-MAC receives packet from PHY BB and transforms it in
several blocks like the hardware 128bit advanced encryption
standard (AES) unit which benefits from the implementa-
tion described in Figure 7, CRC generation/verification units
top-level finite state machine is the intelligence behind the
flow between SW-MAC and PHY BB depending on the type
of configuration defined by the SW-MAC.
The block diagram of the HW MAC depicting the flow
of data between SW-MAC and PHY BB is shown in Figure 7.
The presence of HW-MAC makes the SW-MAC perceive the
PHY layer as any other peripheral. This is because the HW-
MAC provides the SW-MAC with an interface similar to a
memory. Various configurations and status registers includ-
ing the data and header FIFOs are mapped on to an address
space to which the SW-MAC can write. If the SW-MAC re-
quires transmitting a data packet over the air, it writes the
configuration in the registers and the data to be transmitted
into the FIFOs. The HW-MAC delivers it to the PHY layer
according to the configuration set by the SW-MAC. Con-
versely, when a packet is received from the PHY layer and if it
is intended for a device in receive mode, the HW-MAC ver-
ifies the packet for its integrity and interrupts the SW-MAC
to inform about the received packet. Besides these schedul-
ing functions, the HW-MAC also implements primitives to
CRC generation/verification, and other minor functions like
packet parsing, packet formatting, timers, and so on.
Like any OFDM system, the M-HDR air interface is sensi-
tive to synchronization error and a particular attention has
been made to handle robust synchronization at the receiver.
Another specific concern for real-time digital design of the
M-HDR air interface is clock-domain management. Finally,
hardware implementation errors (e.g., quantization noise,
operator bias, etc.) impact on processing precision needs to
be quantified. Implementation loss induced by the baseband
processing is scarcely addressed in the literature. In this sec-
tion, the error introduced by the digital baseband processing
is quantified and its impact is given in terms of equivalent
additive white Gaussian noise (AWGN) signal on the ideal
Thesynchronization aimsatreferencingin timetheFFTvec-
tor for OFDM demodulation and at estimating the carrier
frequency offset (CFO) in the time domain (pre-FFT). CFO
ing the CFO is of paramount importance for OFDM systems
which are very sensitive to such an impairment . Synchro-
nization is processed on the fly and runs continuously once
the AGC is locked. It seeks a specific synchronization pattern
contained in each frame header . The synchronization
updated every received sample. It synchronizes the data flow
according to the strongest path of the channel which is used
as time reference.
The time synchronization is performed as follows. First,
the autocorrelation of the received signal is computed. The
periodic nature of the synchronization pattern enables the
autocorrelation to show a typical flat region when the syn-
chronization symbol is received. When the flat region is de-
tected, the synchronization sample is coarsely indexed. To
refine the position detection, a more restricted window is
considered and the cross-correlation of the input signal with
the known synchronization pattern is analyzed throughout
this window. Peaks appear on the cross-correlation profile as
soon as the known pattern is completely received. As previ-
ously stated, criterion to detect those peaks is defined. When
last cross-correlation peak is received, the system can be syn-
chronized accurately. In fact, the window is active when the
autocorrelation signal is higher than the threshold over more
than a predetermined time. This time is related to the syn-
chronization pattern duration.
In order to determine the best threshold value, the syn-
chronization Probability of false alarm (PFA) or that of mis-
detection (PMD) is analyzed. The PFA and PMD as a func-
tion of the autocorrelation threshold is given in Figure 8 for
6EURASIP Journal on Wireless Communications and Networking
Figure 7: HW-MAC block diagram.
False alarm and misdetection probability
Auto correlation threshold
PMD SNR= 2dB
PMD SNR= 8dB
PMD SNR= 14dB
PMD SNR= 4dB
Figure 8: False alarm and misdetection probability.
PMD SNR= 10dB
PMD SNR= 6dB
PMD SNR= 12dB
age of the maximum value of the autocorrelation.
The PFA is defined as the probability of finding a syn-
chronization sample while no synchronization symbol was
transmitted. Obviously, it decreases when the autocorrela-
tion threshold increases. The PFA does not depend on the
signal-to-noise ratio (SNR). This is due to the fact that the
flat region is never detected when no synchronization pat-
tern is sent, whatever the noise level.
The PMD is defined as the probability of missing the
synchronization point despite the transmission of a synchro-
nization symbol. For the lowest thresholds, the misdetection
is mainly due to bad flat region localization or, as for the
false alarm, due to the absence of autocorrelation flat re-
gion falling edge. For high thresholds, misdetection is also
high but mainly due to nondetection of the flat region. Be-
tween these two threshold regions, a minimum is obtained
A PFA versus PMD, tradeoff values can be obtained for
each SNR as the crossing point of the misdetection and false
alarm curves. For instance, the SNR = 8dB provides PFA <
10−5and PMD < 10−5choosing the threshold equal to 68%.
When higher SNR are targeted, increasing the threshold will
reduce the false alarm probability. For 10dB, setting a 70%
threshold brings about PFA < 10−6and PMD < 10−6.
Bringing flexibility of the baseband in terms of data rate in-
creases the complexity of clock management. This section
describes clock management and its impact on hardware ar-
chitecture tradeoffs. The focus is on the 40MHz system but
can be transposed to the 20MHz case easily. The convolu-
tional encoder is fed with data at frequency f . The coder
produces two parallel bits which are serialized before being
punctured. Let N be the number of bits per symbol, D the
serial output data rate of the convolutional encoder, R the
global code rate, P the puncturing rate, and f the working
frequency if only one frequency was used in the design. Since
each OFDM symbol of 266 samples carries 192 data, the se-
rial bitrate at the output of the coder is D = 192 × 40 ×
N/266 ≈ 29×N.Attheoutputofthepuncturing,thedataare
at the frequency f. Table 2 recaps the frequency to be used
at the coder module according to the MAGNET modulation
scheme implying different clock frequencies. The solution to
is to use XILINX Virtex 4 tunable DLL feature.
Although the interleaver is processing bits, it is using a
parallel architecture whose width is determined by the one
of a symbol. This results in an operating frequency of D/N =
29MHz. This parallel approach was chosen due to frequency
requirements for real-time operation. A serial implementa-
tion would indeed have had to sustain 174MHz operation
rate in the worst case. Thus, the parallelization, which is typ-
ically performed before the mapper here sources the input of
the interleaver. In order to simplify clock management, the
Dominique Noguet et al.7
Table 2: Convolutional encoder frequencies.
Nb bit/OFDM symbol
174/6 = 29MHzFraming
FIFOS→P Interleaver Mapping
f and f/2
174/6 = 29MHz
Bit level signal
6 bits level signal
Figure 9: M-HDR baseband clock management.
serial to parallel converter always works at the highest fre-
quency, and the data validation signal duty cycle is adjusted
part of the design working at high frequency that does not
need to be changed according to the modulation. The map-
per and the spreader, that follow, process at the modulation
symbol rate, namely, 29MHz. Then, pilots are inserted in-
creasing the rate up to 40MHz for the OFDM modulation.
Figure 9 shows the resulting clock domains.
5. RF FRONT-END
For the M-HDR platform, several receiver front-end archi-
tectures have been considered, two of which have emerged as
possible candidates. On one hand, a classical zero interme-
diate frequency (zero-IF), and on the other hand, a modi-
fied weaver  which achieves a rejection of the image fre-
quency, are generated by the down conversion of a hetero-
As it is known, the weaver architecture is first mixed with
the quadrature phases of the local oscillator to be then low-
pass filtered (see Figure 10, in which IF = RF1− LO =
LO −RF2, where RF1is the desired signal and RF2the image
frequency that would lead to the same IF after the synthesis).
problem of a secondary image, if the second mixer translates
the spectrum to a nonzero frequency. With the frequency
UMTS image frequency to interfere with the desired signal.
The performance of the modified weaver architecture in
terms of rejection depends on the phase and gain mismatch
between the two reception paths. For a 1–5◦phase mismatch
or 0.2–0.6dB gain mismatch, it was reported that such archi-
tecture achieves 30–40dB rejection .
The parameters of the second approach, the zero-IF-
based architecture, are specified in Figure 11. The global
noise factor is similar to the one of the weaver architecture.
In this case, the potential interference will come from the
IEEE802.11 systems due to the direct convertion nature of
this architecture. Therefore, rejection filtering concerns fall
on this WLAN system. The filtering contribution is shared
between the radio frequency (RF) filter, the analog baseband
8EURASIP Journal on Wireless Communications and Networking
3.6GHz (0◦)1.6GHz (0◦)
3.6GHz (90◦)1.6GHz (90◦)
NFtotal = NF0+NF1−1
Figure 10: Weaver RF architecture.
Noise figure (loss): 0.5dB
Phase Error: 0.5
Gain error (imbalance): 0.1dB
Impedance: (matched to LNA)
Noise figure: 1.5dB
Adjacent channel rejection: 30dB
Noise figure: 20dB
Adjacent channel rejection: 30dB
Noise figure: 5dB
1dB compression point: −25dBm
Phase error: 20 (discrete)
Gain error: 0.2dB
Noise figure: 8dB
LO to RF: 30dB
LO to DC: 27dB
RF to DC: 40dB
Phase error: 20
Gain error: 0.2dB
A.N.: NFtotal = 5.2dB
NFtotal = NF0+NF1−1
Figure 11: Zero-IF RF architecture.
nel and image coincide due to the direct conversion, the
zero-IF architecture does not suffer from image rejection is-
sue. This latter point is more critical for the weaver archi-
tecture that implements an “explicit” rejection scheme. The
conclusion that can be drawn is that provided the same fre-
quency selectivity for the filtering after the low-noise ampli-
jection capability, though the weaver architecture requests a
sical drawback of the zero-IF-architecture is the DC offset,
since this imperfection is translated to the baseband by the
Dominique Noguet et al.9
16MB flash + 64MB SDRAM
Digital boardRF board
Figure 12: Platform block diagram.
Figure 13: M-HDR prototype: (a) digital side and host PDA; (b) RF daughter board side and antenna.
Bit error rate
8 10 1214
Floating point (simulation)
Fixed point (prototype)
Figure 14: Impact of fixed point computation for noncoded QPSK
direct conversion. However, since the DC subcarrier is not
sue if enough attention is paid to the frequency stability and
Bit error rate
1214 16 18
Perfect channel and CFO (ref.)
With CFO estimation
With channel estimation
With channel and CFO estimation
Figure 15: Impact of CFO and channel estimation for noncoded
The phase noise is imposed on each OFDM subcarrier by
the RF synthesis. The phase noise is generated by the RF fre-
quency synthesis of phase locked loop (PLL) and mixed with
the RF signal, thus affecting downconverted baseband signal
10EURASIP Journal on Wireless Communications and Networking
Bit error rate
QPSK 1/2 baseband
QPSK 1/2 baseband & RF
Figure 16: Impact of RF front-end for QPSK-1/2 configuration.
by a random phase shift in the time domain (before FFT).
The influence of the phase noise in the OFDM signal appears
in two different ways in the frequency domain as reported in
(1) A common phase error (complex value) is multiplied
to all subcarriers. This error comes from close-to-
carrier phase noise. This error can be tracked and re-
moved by equalization.
(2) Due to further carrier phase noise, subcarriers are
mixed together at FFT process, by such a way, inter-
carrier interference appears as hardly removable extra-
noise in the signal.
These should lead to a tradeoff between signal processing ex-
ments on the PLL and crystal choices.
Innovative design works [14–17] presented different
techniques that provided improved reliability and a yield of
CMOS RF transceivers, what has made, after the proper evo-
lution in the research areas, CMOS process a real player in
the cost-effective radio market. Single-chip solution offers as
well several advantages such as reduction in manufacturing
and packaging costs due to the elimination of the routing be-
board (PCB) multilayer complexity reduction. Smaller ar-
eas and diminished consumption (simplification of internal
interfaces between blocks) jointly with shorter factory test
times and higher test yields are other benefits of the single-
chip designs. For these reasons, the zero-IF approach was
preferred and the MAXIM MAX2829 chip was used as the
heart of the RF part of the design. Besides, the included PLL
bandwidth and the chosen crystal reference made negligible
the extradistortion caused by the phase noise effects.
The M-HDR prototype consists of a set of boards that em-
bed the components needed for the implementation of MAC
and PHY layers, namely, an RF board implementing TX
and RX RF functions from/up to the converters up to/from
the antenna and a digital board implementing digital PHY
and MAC functionalities. The latter also includes some host
bridging features in order to plug the HDR prototype to a
host device. An overview of the M-HDR prototype is illus-
trated in Figure 12.
The HDR RF subsystem (or board) is based on an
off-the-shelf component from MAXIM (MAX2829). The
MAX2829 is designed for dual-band 802.11a/g applications
covering especially world-band frequencies of 4.9GHz to
5.875GHz. The IC includes all circuitry required to imple-
ment the RF transceiver function, providing a fully inte-
grated receive path, transmit path, VCO, frequency synthe-
sizer, and baseband/control interface. Only the power ampli-
fier, RF switches, RF bandpass filters (BPFs), RF baluns, and
a small number of passive components are needed to form
the complete RF front-end solution.
The digital board houses the programmable chips
that implement baseband PHY and MAC functions.
For SW-MAC primitives, an ARM9 has been selected
(AT91RM9200). The SW-MAC primitives run on top of a
Linux OS. For the HW-MAC and PHY primitives, a Xilinx
Virtex 4 has been chosen due to hardware resource available
and flexible clock management capability (XC4VSX55-10).
Complexity analysis that led to this chipset choices is pro-
vided in Table 3. The NIC is used by its host as a USB device.
Battery operation was made possible to enable handheld
field trials. It offers autonomy of several hours. Power con-
sumption is mainly due to FPGA implementation though
an equivalent system-on-chip implementation would yield
to dramatic power consumption decrease.
7. PHY MEASUREMENT RESULTS
This section aims at providing results of the tests performed
with the M-HDR prototype. The first tests consist in bit er-
ror rate (BER) versus SNR for different configurations of the
platform, gradually illustrating the impact of each approxi-
mation. Results presented hereafter are all given for AWGN
channels for the sake of comparison.
The first step aims at evaluating the impact of fixed point
implementation within the FPGA. It is worth mentioning
that the converters (ADC) at the input of the receiver have
a 12bit dynamic introducing a quantization SNR of 72dB.
This means that the conversion noise is negligible within the
SNR range addressed by the receiver. In order to see the im-
pact of fixed point computation, the BER vresus SNR per-
formance of the prototype was compared with the floating
point simulation model. In both cases, measurements are
performed under perfect channel estimation and without
Figure 14 for AWGN channel. From these noncoded perfor-
mance curves, it can be noted that performance loss is negli-
gible at the SNR range to be considered for the system.
Results provided hereafter are coming from prototype
totype. The equalizer coefficients use a 12bit quantization
without additional performance impact due to quantization
Dominique Noguet et al. 11
Bit error rate
468 1012 14
Bit error rate
With mismatch and correction
Figure 17: Impact of (a) IQ mismatch (lin/rad) and (b) IQ mismatch correction.
Table 3: Complexity analyis.
PHY/MAC HW (FPGA)
Required for TX baseband
Required for RX baseband
Multipliers (18 ×18)
Block RAM (18kb)
Clock domains (DCM)
Requires for MAC
∼180 to 200MIPS
noise. The previous curve obtained with perfect estimation
is given as a reference. This reference curve is similar to the
one of Figure 14.
It can be observed that the major degradation is brought
by the channel estimator linked to the zero-forcing equal-
izer. However, the 3dB shift is rather due to the kind of esti-
mator chosen rather than its implementation, since floating
point simulation provides similar results. It can be noticed
that the CFO estimation and correction have little impact on
the overall performance.
Measurements presented in Figure 16 show the impact of
some degradation (e.g., around 1.5dB shift at BER of 10−6).
At high SNR, an error floor of 10−8cannot be overtaken.
Such error floor will impact the performance even further
when weaker channel coding schemes will be used. Among
the potential explanation for this phenomenon is the impact
of IQ mismatch. IQ mismatch compensation schemes have
been presented in the literature [13–15]. Simulations have
provided information on the effects of the IQ mismatch and
the frequency offset, as well as the capabilities of the correc-
In the simulation results presented in Figure 17(a), the
white noise coming from IQ mismatch intercarrier interfer-
ence is higher than the front-end thermal noise. Error floor
effects are then similar to those observed on the prototype.
Results show a good BER improvement with IQ mismatch
correction, even if IQ mismatch estimation is degraded at
low SNR. In Figure 17(b), the corrected system curve meets
the “no mismatch” curve.
The multicarrier spread spectrum prototype presented in
this paper enables to achieve data rates that cover most
WPAN applications necessities. Since the WPAN transceivers
are likely to equip battery-operated devices, it is important
that hardware complexity remains reasonable. The MC-SS
air interface described herein has a complexity which is close
to that of WLAN transceivers while achieving better robust-
ness over WPAN channel conditions.
Many hardware-related tradeoffs had to be made for
the implementation. The presented choices have shown
that reasonable implementation loss was caused while hard-
ware complexity was kept as low as possible. Preliminary
12EURASIP Journal on Wireless Communications and Networking
measurements have shown that the degradation introduced
by the baseband implementation is compliant with simula-
tion results. Measurements including the RF show that some
error floor appears at high SNR values. Among the potential
sources of degradation is the IQ mismatch. This impairment
can be compensated at the baseband by efficient correction
schemes that already proved their effectiveness through sim-
This work has been done in the frame of the MAG-
NET Beyond European IST project of the 6th Framework
Program. MAGNET Beyond is an R&D project within
Mobile and Wireless Systems and Platforms Beyond 3G
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The 2011 European Signal Processing Conference (EUSIPCO?2011) is the
nineteenth in a series of conferences promoted by the European Association for
Signal Processing (EURASIP, www.eurasip.org). This year edition will take place
in Barcelona, capital city of Catalonia (Spain), and will be jointly organized by the
Centre Tecnològic de Telecomunicacions
Universitat Politècnica de Catalunya (UPC).
de Catalunya (CTTC) and the
EUSIPCO?2011 will focus on key aspects of signal processing theory and
litili t d b lAt applications as listed below. Acceptance of submissions will be based on quality,
relevance and originality. Accepted papers will be published in the EUSIPCO
proceedings and presented during the conference. Paper submissions, proposals
for tutorials and proposals for special sessions are invited in, but not limited to,
the following areas of interest.
fb i iill b b dlit
Technical Program Co?ChairsTechnical?Program?Co Chairs
Areas of Interest
• Audio and electro?acoustics.
• Design, implementation, and applications of signal processing systems.
ldld• Multimedia signal processing and coding.
• Image and multidimensional signal processing.
• Signal detection and estimation.
• Sensor array and multi?channel signal processing.
• Sensor fusion in networked systems.
• Signal processing for communications.
• Medical imaging and image analysis.
• Non?stationary, non?linear and non?Gaussian signal processing.
Montserrat Nájar (UPC)Montserrat?Nájar?(UPC)
i l Li i& E hibi
Procedures to submit a paper and proposals for special sessions and tutorials will
be detailed at www.eusipco2011.org. Submitted papers must be camera?ready, no
more than 5 pages long, and conforming to the standard specified on the
EUSIPCO 2011 web site. First authors who are registered students can participate
in the best student paper competition.
PProposals?for?special?sessions?l fi l i15 D15?Dec?20102010
Submission?of?camera?ready?papers 6?Jun 2011