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Fast Fourier Transforms on Finite Groups as a Method in Synthesis for Regularity
Abstract
In this paper, we discuss the Fast Fourier transform
(FFT) on finite groups as a tool useful in synthesis for reg-
ularity. FFT is the algorithm for efficient calculation of the
Discrete Fourier transform (DFT) and has been extended to
computation of various Fourier-like transforms. The algo-
rithm has a very regular structure that can be easily mapped
to technology by replacing nodes in the corresponding flow-
graphs by circuit modules performing the operations in the
flow-graphs. In this way, networks with highly regular
structure for implementing functions from their spectra are
derived. Fourier transforms on non-Abelian groups offer
additional advantages for reducing the required hardware
due to matrix-valued spectral coefficients and the way how
such coefficients are used in reconstructing the functions.
The optimization of produced networks with regular struc-
ture can be performed by methods for optimization of spec-
tral representations of functions on finite groups.
... The class of regular lattice networks [2]- [4] is an important class of regular circuits that generalize the ideas from the well-known Akers arrays [1], spectral transform decision trees and decision diagrams [16], [36]- [37], and symmetric networks [31]. Due to high regularity, lattice networks are useful in many applications including fault-related issues such as testing, localization and self-repair. ...
Novel realizations of concurrent computations utilizing three-dimensional lattice networks and their corresponding carbon-based field emission controlled switching is introduced in this article. The formalistic ternary nano-based implementation utilizes recent findings in field emission and nano applications which include carbon-based nanotubes and nanotips for three-valued lattice computing via field-emission methods. The presented work implements multi-valued Galois functions by utilizing concurrent nano-based lattice systems, which use two-to-one controlled switching via carbon-based field emission devices by using nano-apex carbon fibers and carbon nanotubes that were presented in the first part of the article. The introduced computational extension utilizing many-to-one carbon field-emission devices will be further utilized in implementing congestion-free architectures within the third part of the article. The emerging nano-based technologies form important directions in low-power compact-size regular lattice realizations, in which carbon-based devices switch less-costly and more-reliably using much less power than silicon-based devices. Applications include low-power design of VLSI circuits for signal processing and control of autonomous robots.
New implementations within concurrent processing using three-dimensional lattice networks via nano carbon-based field emission controlled-switching is introduced in this article. The introduced nano-based three-dimensional networks utilize recent findings in nano-apex field emission to implement the concurrent functionality of lattice networks. The concurrent implementation of ternary Galois functions using nano threedimensional lattice networks is performed by using carbon field-emission switching devices via nano-apex carbon fibers and nanotubes. The presented work in this part of the article presents important basic background and fundamentals with regards to lattice computing and carbon field-emission that will be utilized within the follow-up works in the second and third parts of the article. The introduced nano-based three-dimensional lattice implementations form new and important directions within three-dimensional design in nanotechnologies that require optimal specifications of high regularity, predictable timing, high testability, fault localization, self-repair, minimum size, and minimum power consumption.
In several publications, the use of non-Abelian groups has been suggested as a method to derive compact representations of logic functions. The compactness has been measured in the number of product terms in the case of functional expressions and the number of nodes, the width, and the interconnections in the case of decision diagrams. In this paper, we discuss Fourier representations on finite non-Abelian groups in synthesis for regularity. The initial domain group for a logic function (binary or multiple-valued) is replaced by a non-Abelian group by encoding of variables. The function is then decomposed into matrix-valued Fourier coefficients, that are easy to implement as building blocks over a technological platform with regular structure. We point out that spectral representation of non-Abelian groups is capable of capturing regularities in functions and transferring them in the spectral domain. In many cases, weak regularities in the original domain are converted into much stronger regularities in the spectral domain due to the regular structure of unitary irreducible group representations upon which the Fourier expressions are based.
This paper considers partial-column radix-2 FFT processors and realizations of butterfly operations. The area and power-efficiency
of butterfly units to be used in the proposed processor organization based on bit-parallel multipliers, distributed arithmetic,
and CORDIC are analyzed and compared. All the selected butterfly units are synthesized onto the same 0.11 μ ASIC technology
allowing the results to be compared. The proposed processor organization permits the area of the FFT implementation to be
traded against the computation time, thus the final structure can be easily tailored according to the requirements of the
given application. The power consumption comparison shows that butterflies based on bit-parallel multipliers are power-efficient
but have limitations on clock frequency. Butterflies based on distributed arithmetic could be used when higher clock frequencies
are used. If extremely long FFTs are needed, the CORDIC based butterflies are applicable.
Applications based on Fast Fourier Transform (FFT) such as signal and image processing require high computational power. This paper proposes the implementation of radix-4 based parallelpipelined Fast Fourier Transform processor which incorporates a low power commutator, butter-fly with multiplier-less architecture. The proposed parallel pipelined architectures have the advantages of high throughput and low power consumption. The multiplier-less architecture uses shift and addition operations to realize complex multiplications.
The authors present a method for an optimal implementation of
general discrete Fourier transform (GDFT) algorithms over finite groups
(Abelian and non-Abelian) in a multiprocessor environment. Tradeoffs
between hardware complexity/speed and computation time are investigated
for different multiprocessor implementations with local nonshared
memories (unibus, complete communication network). Formulas are
presented for the number of arithmetic operations, for the number of
interprocessor data transfers, and for the number of communication links
among the processors
A recent paper by Crimmins et al. deals with minimization of mean-square error for group codes by the use of Fourier transforms on groups. In this correspondence a method for representing the groups in a form suitable for machine calculation is shown. An efficient method for calculating the Fourier transform of a group is also proposed and its relationship to the fast Fourier transform is shown. For groups of characteristic two, the calculation requires only N log_2 N additive operations where N is the order of the group.
Recent works [1]-[9] were devoted to the properties and application of Fourier transforms over finite Abelian groups and fast Fourier transforms for calculation of the corresponding spectra. In this correspondence we describe Fourier transforms on finite non-Abelian groups and appropriate algorithms of fast Fourier transforms.