Low voltage dual mode logic: Model analysis and parameter extraction

Microelectronics Journal (Impact Factor: 0.84). 06/2013; 44(6):553–560. DOI: 10.1016/j.mejo.2013.03.005

ABSTRACT The Dual Model Logic (DML) family, which was recently introduced by our group for sub-threshold operation, provides an alternative design methodology to the existing low power digital design techniques. DML gates allow switching between static and dynamic modes of operation on-the-fly according to system requirements, presenting better tradeoff between Energy consumption and performance. In static mode, low voltage DML gates achieve very low Energy consumption with moderate performance, while in dynamic mode they achieve high performance, albeit with higher Energy consumption. In this paper we analyze DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages. The sizing methodology of low voltage DML is discussed and classical Logical Effort parameters are calculated for the 40 nm DML basic gates. The design example of a DML full adder, implemented in a 40 nm low power standard CMOS technology, is shown to compare the proposed method with its CMOS and Domino counterparts. Monte Carlo simulations are shown to demonstrate the DML immunity to process variations.

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    ABSTRACT: The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to improve energy efficiency and performance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates the design's critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumption reduction. The proposed approach is analyzed on a 128 bit carry skip adder. Simulations, carried out in a standard 40 nm digital CMOS process with , show that the proposed approach allows performance improvement of X2 along with reduction of energy consumption of X2.5, as compared with a standard CMOS implementation. At , improvements of 1.3X and 1.5X in performance and energy are achieved, respectively.
    01/2013; 1:258-265. DOI:10.1109/ACCESS.2013.2262015