Low voltage dual mode logic: Model analysis and parameter extraction
ABSTRACT The Dual Model Logic (DML) family, which was recently introduced by our group for sub-threshold operation, provides an alternative design methodology to the existing low power digital design techniques. DML gates allow switching between static and dynamic modes of operation on-the-fly according to system requirements, presenting better tradeoff between Energy consumption and performance. In static mode, low voltage DML gates achieve very low Energy consumption with moderate performance, while in dynamic mode they achieve high performance, albeit with higher Energy consumption. In this paper we analyze DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages. The sizing methodology of low voltage DML is discussed and classical Logical Effort parameters are calculated for the 40 nm DML basic gates. The design example of a DML full adder, implemented in a 40 nm low power standard CMOS technology, is shown to compare the proposed method with its CMOS and Domino counterparts. Monte Carlo simulations are shown to demonstrate the DML immunity to process variations.
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ABSTRACT: Local voltage dithering provides near optimum savings when workload varies for fine-grained blocks. Combining this approach with sub-threshold operation permits ultra-dynamic voltage scaling from 1.1 V to below 300 mV for a 90-nm test chip. Operating at 330 mV provides minimum energy per cycle at 9× less energy than ideal shutdown for reduced performance scenarios. Measurements from the test chip characterize the impact of temperature on the minimum energy point.IEEE Journal of Solid-State Circuits 02/2006; · 3.11 Impact Factor
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ABSTRACT: This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum V<sub>DD</sub> and V<sub>T</sub> to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum V<sub>DD</sub> for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-μm test chip is used to compare normal sizing and sizing to minimize operational V<sub>DD</sub> and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.IEEE Journal of Solid-State Circuits 10/2005; · 3.11 Impact Factor
Article: Low-power CMOS digital design[Show abstract] [Hide abstract]
ABSTRACT: Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumptionIEEE Journal of Solid-State Circuits 05/1992; · 3.11 Impact Factor