A Performance Comparison Of Four Buffering Schemes For Multistage Interconnection Networks
ABSTRACT Multistage interconnection networks (MINs) are used to connect processors and memories in large-scale multiprocessor systems. MINs have also been proposed as switching fabrics in ATM networks. A MIN consists of several stages of small crossbar switching elements (SEs). A number of buffering schemes are used in the SEs to increase the throughput of MINs and prevent internal loss of packets. the objective of this article is to compare the performance of MINs using different buffering schemes in the presence of uniform and nonuniform traffic patterns. The results obtained from the study will help computer architects and network designers in choosing appropriate buffering strategies for fabric design and configuration of MINs. The normalized throughput, packet loss, and packet mean delay have been used as the performance measures for comparing the different buffering strategies. Results show that the performance of split-shared and output-buffered MINs is considerably better than that of input-buffered MINs when the hot request rate is low. However, the performance is identical for all the buffering schemes when the hot request rate is medium or high.
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ABSTRACT: Banyan Networks are a major class of Multistage Interconnection Networks (MINs). They have been widely used as efficient interconnection structures for parallel computer systems, as well as switching nodes for high-speed communication networks. Their performance is mainly determined by their communication throughput and their mean packet delay. In this paper we use a performance estimation model that is based on a universal performance factor, which includes the importance aspect of each of the above individual performance factors (throughput and delay) in the design process of a MIN. The model can also uniformly be applied to several representative networks. The complexity of the model requires to be investigated by time-consuming simulations. In this paper we study a typical (8X8) Baseline Banyan Switch that consists of (2X2) Switching Elements (SEs). The objective of this simulation is to determine the optimal buffer size for the MIN stages under different conditions09/2007: pages 107-111;
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ABSTRACT: In this paper, we model, analyze and evaluate the performance of a 2-class priority architecture for finite-buffered multistage interconnection networks (MINs). The MIN operation modelling is based on a state diagram, which includes the possible MIN states, transitions and conditions under which each transition occurs. Equations expressing state and transition probabilities are subsequently given, providing a formal model for evaluating the MIN's performance. The proposed architecture's performance is subsequently analyzed using simulations; operational parameters, including buffer length, MIN size, offered load and ratios of high priority packets which are varied across experiments to gain insight on how each parameter affects the overall MIN performance. The 2-class priority MIN performance is compared against the performance of single priority MINs, detailing the performance gains and losses for packets of different priorities. Performance is assessed by means of the two most commonly used factors, namely packet throughput and packet delay, while a performance indicator combining both individual factors is introduced, computed and discussed. The findings of this study can be used by network and interconnection system designers in order to deliver efficient systems while minimizing the overall cost. The performance evaluation model can also be applied to other network types, providing the necessary data for network designers to select optimal values for network operation parameters.Journal of Network and Computer Applications 03/2013; 36(2):723–737. · 1.47 Impact Factor
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ABSTRACT: In future, multicore processors with hundreds of cores will collaborate on a single chip. Then, more advanced network-on-chip (NoC) topologies will be needed than today's shared busses for dual core processors. Multistage interconnection networks, which are already used in parallel computers, seem to be a promising alternative. In this paper, a new network topology is introduced that particularly applies to multicast traffic in multicore systems and parallel computers. Those multilayer multistage interconnection networks are described by defining the main parameters of such a topology. Performance and costs of the new architecture are determined and compared to other network topologies. Network traffic consisting of constant size packets and of varying size packets is investigated. It is shown that all kinds of multicast traffic particularly benefit from the new topology.Computers & Operations Research. 01/2008;