IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 4, OCTOBER 2011 2801
ICT Architecture Impact on Wide Area Monitoring
and Control Systems’ Reliability
Kun Zhu, Student Member, IEEE, Moustafa Chenine, Student Member, IEEE, and Lars Nordström, Member, IEEE
Abstract—Timely and accurate data with high resolutions
holds great promise for more responsible and advanced power
grid operations. The research has been focusing on design of
monitoring and control scheme given the assumptions that the
supporting information and communication technology (ICT)
systems are capable of providing data and perform control with
sufficient quality. A relatively less addressed aspect is the depen-
dency of wide-area monitoring and control (WAMC) systems on
their supporting ICT architecture which is usually a compromise
between various concerns, such as data quality, interoperability,
or security. Without an appropriate ICT architecture design, the
projected WAMC system functionalities run the risk of being
jeopardized. This paper begins with a presentation about pos-
sible delays brought by complex data-transfer and processing
processes. Analytical experiments are conducted with purposes to
quantify the maximum delay and input signal’s sensitivity toward
delay on a typical WAMC application where the control of static
var compensation (SVC) is coordinated with generator excitations
using phasor measurements. Given the characteristics of this
particular control scheme, two possible ICT architectures that
provide data with different qualities are compared concerning the
reliability of this WAMC application. This paper concludes by
proposing a generic ICT architecture, enabling efficient WAMC
systems implementation in terms of data quality.
Index Terms—Delay, information and communication tech-
nology (ICT), phasor measurement, SVC, wide-area monitoring
and control (WAMC) systems.
phasor measurement unit (PMU)-based monitoring and control
technology , . These systems promise to offer more
accurate and timely data on the state of the power system and,
thus, also increase possibilities to manage the system at a more
efficient and responsive level . These systems are needed in
the modern electrical power system, where network expansion
is limited by monetary and environmental regulations. The
increased dependency on the ICT systems and their capabilities
to provide correct functionality triggers a need to address ICT
concerns in design stage of wide-area monitoring and control
HERE is an international interest and implementation
drive, in academia and industry, in the perspective of
Manuscript received March 16, 2011; accepted June 22, 2011. Date of pub-
lication August 12, 2011; date of current version October 07, 2011. Paper no.
The authors are with the Department of Industrial Information and Control
Systems, Royal Institute of Technology (KTH), Stockholm SE-10044, Sweden
(e-mail: firstname.lastname@example.org; email@example.com; firstname.lastname@example.org).
Color versions of one or more of the figures in this paper are available online
Digital Object Identifier 10.1109/TPWRD.2011.2160879
of hardware and software components of different types com-
functional factors, such as data delay and losses contributed by
inappropriate ICT solutions, run the risk of jeopardizing system
function execution , . The failure rate of WAMC systems,
paper, could be traced back to either the insufficiency of the in-
dividual ICT components or the inappropriate ICT architecture
A. Scope of the Paper
This paper presents a case study demonstrating the depen-
dency of WAMC application reliability on supporting ICT
system architectures, with a focus on data delay and losses.
The consequence of input data with insufficient quality caused
by inappropriate ICT architecture design in WAMC systems is
presented and the performance requirements posed on the sup-
porting ICT systems are elicited. Furthermore, a generic ICT
architecture enabling large-scale implementation of WAMC
systems is proposed in this paper.
The rest of this paper is structured as follows. Section II
presents an overview of WAMC system architectures out-
lining the major components of these systems. Section III
presents possible delays in supporting ICT systems for WAMC
applications. Section IV describes the simulation model
implementations and Section V explains the parameters in
experiment scenarios. The analysis of simulation results and
a discussion can be found in Sections VI and VII. Finally, the
paper is concluded in Section VIII.
II. ICT COMPONENTS OF WAMC SYSTEMS
A WAMC system includes four basic components: 1) PMU,
2) phasor data concentrator (PDC), WAMC application, and,
finally, communication networks . Fig. 1 illustrates the basic
logical architecture of WAMC systems.
1 through the PMUs connected to substation busbars or power
where the PMU measurements are collected and sorted as syn-
chronized datasets with time stamps by the PDC. Afterwards,
the processed data are forwarded to the WAMC applications on
abled by the communication networks.
0885-8977/$26.00 © 2011 IEEE
2802 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 4, OCTOBER 2011
Fig. 1. Layers and components of the WAMC system.
Fig. 2. Unified and integrated ICT architecture versus “Stove-pipe” architec-
The communication infrastructure is a potential bottleneck in
the architecture of WAMC systems. This is because PMU de-
vices in most cases are geographically scattered overlarge terri-
tories. The phasor data are either subscribed locally or uploaded
to units which are located at an upper level of the operation
hierarchy over communication networks depending on opera-
tion concepts and organizations. Therefore, the data quality of
phasor measurements collected from the remote sites highly de-
pends on the communication infrastructure’s quality of service
Generally, when designing supporting ICT systems for
WAMC applications, it is more convenient to have a unified
and integrated architecture where all phasor data are processed
and disseminated in a similar fashion as opposed to each
application having its own dedicated concentration and phasor
data processing. The latter approach creates a situation which
is similar to the notorious “Stove-pipe” architecture . The
unified solution has many advantages, such as lower costs,
ease of maintenance, and flexibility of reconfigurations. Fig. 2
illustrates these two architectural scenarios graphically.
III. DELAYS IN WAMC SYSTEMS
Real-time WAMC systems put stringent time requirements
in terms of data delay in comparison to the conventional
Fig. 3. Utility communication model, showing substation local-area network
(LAN) and control center LAN connected by the wide-area network (WAN).
SCADA/EMS solutions in order to identify, analyze, and
respond to emergency phenomenon in the power system in a
more responsible and accurate manner , . The delay of the
WAMC system can be traced back to the involved processes
and components according to the system architecture presented
in the previous section. Particularly in this paper, the studied
delay sources are data propagation and data sorting at PDC.
The communication infrastructure in this part is simplified as
illustrated in Fig. 3.
The PMUs or controllers are deployed at substations, con-
nected to a local-area network (LAN). The substation LAN is,
in turn, connected via a substation router to a wide area network
plications are dependent on data from several PMUs, the phasor
measurements are first uploaded to PDC for sorting after which
they are forwarded to applications. If it is a control application,
the generated control commands are transferred via the WAN to
the substations where the controllers are located. It is necessary
to clarify that depending on the needs of the applications, the
PDC and applications are not required to be implemented at the
A. PDC Sorting Function
The most basic function of the PDC is to collect or receive
phasor measurements from connected PMUs and to sort them
according to the global positioning system (GPS) time stamps.
Once a data packet containing all phasors with the same time
stamp is complete, the PDC forwards a phasor set to the appli-
cations where the data are subscribed. The PDC could also have
other functionality, such as error checking and archiving for of-
fline and historical data analysis . In this paper, only the time
consider them confidential. On the other hand, the main-time
synchronization algorithm can be derived from descriptions, to-
gether with actual requirements of the sorting and synchroniza-
tion tasks .
In this generic algorithm, the PDC will group together mea-
surements from the same time stamp into a set. This is done
as the measurements arrive at the PDC. With the purpose of
mitigating delays, a time-out per time stamped buffer is added.
The time out would be the amount of time the buffer is actively
waiting for the remaining phasor measurements with the same
time stamp. The countdown to the time out is initiated when
the first phasor measurement of a certain time stamp arrives at
ZHU et al.: ICT ARCHITECTURE IMPACT ON WIDE AREA MONITORING AND CONTROL SYSTEMS’ RELIABILITY 2803
Fig. 4. Time-stamped buffers in the PDC holdingmeasurements in alinked list
Fig. 5. Test bed including the reference network with the SVC control scheme
and supporting ICT systems.
the PDC. The PDC assigns this newly arrived measurement to
a new buffer, and begins the time-out counter for that buffer. In
this case, when the time-out is up, the PDC will forward the set
of available data without waiting for the remaining phasor mea-
surements to arrive.
The time-out parameter introduces a ceiling in terms of the
delay that can be experienced and is deterministic. If the PMU
communication network were to experience abnormal delays or
packet loss, then the waiting time parameter ensures that the
PDC forwards the phasor measurements in an acceptable time
range without waiting for the delayed measurements to arrive.
Fig. 4 illustrates this algorithm. On the other hand, the issue of
data losses occurs when data packets with empty data slots are
forwarded to the applications.
B. Data Propagation and PDC Sorting Delay
as the transmission time through WAN including routing delays
Fig. 6. Voltage profiles at the regulated bus given the delayed POD signal and
perfect voltage measurement (Scenario I).
depends on the following parameters:
• when it arrives (early packets have to wait until all packets
from the same timestamp have arrived);
• how many PMUs are being sent (more PMUs to wait for);
• how long to wait for the last PMU packet for that time
• time-out setting
• time spent on sorting data in the PDC
This linked-list sorting algorithm can be described as
from the PMUs to the PDC . In the implemented algorithm,
the PMU packet with the longest transmission time
mines the maximum time that all packets will have to wait
represents the peer-to-peer data propagation delay
from the discussion, a complete expression
can be derived as
to study the characteristics of
tectures and with different settings for
riencing various amounts of delay, a simulation study was per-
formed. The description of the test is presented in the following
in different system archi-
in networks expe-
IV. TEST-BED IMPLEMENTATION
The test-bed implemented in this paper is a combination of a
power system simulator where consequences of WAMC system
performance giving insufficient data qualities can be evaluated
together with a supporting ICT system where data-quality char-
for the power system simulation in this paper. The supporting
ICT system of WAMC systems, particularly the communica-
tion network and the PDC sorting algorithm, are studied given
a simulation implemented in OPNENT . The power system
one-line diagram, together with ICT components, is presented
in Fig. 5.
2804 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 4, OCTOBER 2011
A four-machine two-area system from Kundur is used as the
reference network model. The model consists of two fully sym-
metrical areas that are connected by two parallel 220-kV trans-
mission lines. Two identical round rotor generators are located
in each area, respectively. The network model and its detailed
parameters can be found in  and . A static var compen-
sator (SVC) is deployed for voltage regulation controlling the
reactive power injections at the connected point. There are dif-
ferent models to describe SVC dynamic performance. In this
paper, the automatic voltage regulator (AVR) model is adopted
and its scheme can be found in . The single-machine infi-
nite bus (SMIB) equivalent method is applied to transform the
trajectories of this four-machine power system into the one of a
single-machine equivalent system . In this case, Gen1 and
Gen2 are assumed to be critical machines that are responsible
for loss of synchronism. The global power system states col-
lected by PMUs are used to coordinate the controls between
SVC and the generator excitations.The objective of this work is
WAMC systems’ reliability. There are other alternatives which
could possibly improve thefunctional reliability of WAMC sys-
tems, such asdesigning delay-robustalgorithms. The study
of this paper only focuses on the ICT part that enables the con-
trol scheme rather than the implantation of more advanced al-
Oscillation damping signal and voltage measurement from
the regulated bus are the inputs to this control scheme. There is
one PMU placed at each generator bus to collect rotor speed
and acceleration power , the mismatch between the mechan-
ical powers that turbine takes in, and the generated power. All
and from four generators are used to compute the power
oscillation damping (POD) signal. The voltage at the regulated
bus is measured by another PMU. The PMUs are bound to their
geographic locations whereas the PDCs and the WAMC appli-
cation server for coordination between the SVC and generator
excitations can be freely placed. This brings in the possibility to
restructure the supporting ICT systems.
V. SIMULATION SCENARIOS AND PARAMETERS
In WAMC systems, there are computation processes for de-
cision making which can be either integrated with the actuator
as a distributed control design or placed at centralized locations
as a centralized solution. The latter architecture implies that all
back to the controllers scattered all over the network. Unlike the
local control in the distributed system, the delay in wide-area
power systems could reach a significant number depending on
the ICT system architecture and implementations. Thus, it is
very important to address performance of supporting ICT in-
frastructure into considering the design and implementation of
WAMC systems as such .
A. Delay Sensitivity Analysis
sign stage of such a supporting ICT system, sensitivity analysis
is sensitive to delay. The analysis outputs serve as indications to
Fig. 7. Voltage profiles at the regulated bus given a perfect POD signal and
delayed voltage measurement (Scenario II).
distribute ICT resources. The measurements that are vulnerable
to delay should be prioritized to ensure quality of service.
Iterative simulations are conducted by applying increasing
delays until the WAMC system fails. Thereafter, the perfor-
mance requirement to design a robust remote signal-based SVC
control, in this case, the maximum tolerated delay, could be de-
cided. As described in the previous section, there are, in total,
five phasor measurements involved in this coordinated control
scheme and four phasor measurements collected at the genera-
tors are used to compute the POD signal and one PMU is placed
at the SVC bus to monitor the voltage phasor. To investigate ro-
bustness of the POD signal and voltage measurement to their
corresponding delays, the sensitivity analysis is conducted on
first scenario, it is assumed that only the POD signal calculated
by measurements from four PMUs at generator buses is experi-
encing the delay while voltage measurement is perfect in time.
The simulation results are presented in Fig. 7.
It can be observed that the system even experiences a smaller
oscillation when the PMU measurement suffers a time delay of
delay.Toinvestigate theimpactof PODsignal delay,itis neces-
sary to detect a thresholdfor the delay beyondwhichthe control
function would collapse. Until the delay reaches a value of 300
ms, which is unlikely to be experienced in the four PMU simu-
lation scenarios according to , the system remains stable. It
can be concluded that the damping signal is rather robust to its
The same investigation is performed on scenario II where the
PMU voltage measurement at the SVC regulated bus (Bus 9) is
of no time delay, 47.5-ms delay, and 65-ms delay are plotted in
The oscillation grows as the delay increases. Given itera-
tive simulations, the tolerated delay of voltage measurement is
below 65 ms. Comparing the simulation results from Scenario
I, it is obvious that voltage measurement reacts much more sig-
nificantly to its delay compared to the other measurements. The
observations here indicate that the voltage phasor at the regu-
lated bus is a critical measurement which needs to be prioritized
in terms of ICT resources to ensure reliable control application.
ZHU et al.: ICT ARCHITECTURE IMPACT ON WIDE AREA MONITORING AND CONTROL SYSTEMS’ RELIABILITY 2805
Fig. 8. ICTsystemarchitectureIfortheWAMCsystem, includinginformation
flows within the processes.
B. Supporting ICT System Architectures
In the simulation, the SVC control actuation is based on in-
formation from four PMUs placed at generator buses together
with one PMU located at bus 9. The phasor data are collected
from the PMUs which are geographically scattered and trans-
ferred via a wide-area communication network to PDCs. PDC
sorts the data with the same time stamp into a packet and for-
wards the packet to applications where centralized coordination
and computation are executed. The generated control signal is
then sent to the SVC controller again through the WAN.
In this paper, two ICT architectures are presented and com-
perfect data. For these two ICT architectures, the involved com-
ponents are identical, the only difference is with regard to the
number of PDCs. In ICT architecture I, there is only one PDC
in the system while there are other WAMC applications imple-
mented and executed in parallel. This universal PDC serves to
sort the data for all of the applications which contributes to a
centralized monitoring/control solution. Corresponding to this
requirement, the PDC is placed in a centralized location where
all phasor data are uploaded to s an application neutral solu-
tion. Alternatively, ICT architecture II represents a distributed
solution where several PDC units are deployed and there is one
dedicated PDC located close to the SVC to minimize delay of
this critical measurement as identified in the previous section.
The conceptual layout of the ICT infrastructure I and II are pre-
sented in Figs. 8 and 9, receptively.
C. PDC Delay Scenarios and Parameters
The four PMU scenario simulation results from  are
adopted. Two parameters were varied in order to create a set
of scenarios based on these variations. The parameters that are
varied in the ICT system scenarios are:
• the delay experienced by measurements (from the PMU)
travelling to the PDC
• the time-out parameter
waiting time at the PDC.
is chosen as in Table I and it is used
in conjunction with two main delay parameters. The delay pa-
that determines the maximum
Fig. 9. ICT architecture II for WAMC systems to improve system robustness
including information flows within the processes.
TIME-OUT PARAMETERS ?
NORMAL DELAY DISTRIBUTION PARAMETERS
rameters are used to represent delay behaviors in the transmis-
sion of phasor measurement packets from PMUs to PDCs. The
delay parameter is a mean and variance input to a normal proba-
from the distribution. These values are assigned to every packet
that is sent to the PDC. Table II illustrates the two delay param-
eters used in the simulation.
The base mean and base variance are selected from the pre-
vious work aimed at studying transmission delay in communi-
cation networks for WAMC systems . This delay parameter
is selected to be the standard or base in the simulations. The ex-
tended mean and extended variance are calculated for usage, as
values to represent the case of abnormal delays that could be
experienced in high-speed power system communication net-
works. The extended delay is applied to a specific number of
PMUs rather than all PMUs in any given scenario. This is done
to represent the possible delay only from a subset of PMUs that
could have been a result from various network or hardware con-
ditions, such as increased traffic on the network segment where
the PMUs with extended delay are placed. Finally, by using the
combination of delay and time-out parameters, the number of
four PMUs. Six scenarios each with a value from the time-out
parameters, outlined in Table I, and the delay parameter with a
normal distribution with the base values in Table II. The other
six scenarios have the same parameter except that one of the
PMUs is delayed with the extended normal distributed delay
2806 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 4, OCTOBER 2011
FOUR PMU SCENARIO PARAMETER SETTINGS
Fig. 10. Voltage profiles at the regulated bus given delayed phasor data from
all PMUs with ICT architecture I.
using the extended delay parameters. Table III illustrates this
VI. SIMULATION RESULTS
Iterative simulations are conducted by applying increasing
delays until this SVC and generator excitation coordination
function fails. Thereafter, the performance requirement to
design a robust remote signal-based SVC control, in this case,
the maximum tolerated delay, could be decided.
A. Data Delay and Losses for ICT Architecture I
It can be observed in Fig. 10 that the oscillation grows as
the delay increases. After the delay reaches 69 ms, oscillation
cannot be cancelled by SVC. Therefore, for this particular net-
work and WAMC control paradigm, the maximum tolerated
delay is 69 ms, which poses a latency requirement on the sup-
porting ICT system.
As described in the previous section, phasor data that arrive
later than the selected PDC waiting time
This mechanism contributes to data losses. When a stochastic
is used, the probability of losing data can be illus-
are to be taken independently. This random data loss poses sig-
nificant challenges to the grid operation and control. To enable
the calculation of WAMC applications, there is a need to sub-
stitute the empty data slots in the phasor packet with values.
The most straightforward method is to adopt the latest avail-
able data. If data loss is compensated by this mechanism, as the
delay proceeds, the data losses problem will ultimately turn into
will be ignored.
Fig. 11. Dependency of data incompleteness probability and the selection of
PDC waiting time.
a data-quality issue and the performance of SVC functionality
SVC system reliability and selection of PDC waiting time
can be expressed as
PMU given a time-out parameter.
ensure reliable SVC function and
is an indication that the maximum data loss in a row
can occur without interfering with WAMC system reliability.
According to the study of input signal delay robustness,
voltage measurement has a dominating impact on the overall
system performance whereas other PMU data used to calculate
given input delays. Taking a data resolution of 30 samples/s,
the reliability of this particular SVC application can be ex-
pressed as a function of probability of voltage measurement
represents the probability of data loss for every
is the maximum delay to
is the phasor data resolu-
In paper , the minimum delay that can be experienced
in wide-area communication network can be approximated as
15 ms (the approximation is made by using the mean value of
delay distribution instead of the stochastic delay model). As a
result, the largest possible PDC time-out parameter can be de-
ducted as 54 ms. A further increase of waiting time will lead
to intolerable data delay which invalidates the control function.
Using 15 ms and 54 ms as lower and upper boundaries, only
the valid time-out cases presented in  are selected and pre-
sented in Table IV. In , the presented data-loss probability
corresponds to entire data packet which contains four phasors.
The probability of losing this single voltage measurement is a
quarter of this value. By applying (5), the reliability of the con-
trol function in associationwith PDC waiting time selection can
be calculated. See Table IV for the results.
ZHU et al.: ICT ARCHITECTURE IMPACT ON WIDE AREA MONITORING AND CONTROL SYSTEMS’ RELIABILITY 2807
WAMC APPLICATION RELIABILITY
Fig. 12. Voltage profiles at the regulated bus given the delayed phasor data
from all PMUs with ICT architecture II.
B. Data Delay and Losses for ICT Architecture II
For this particular architecture, since the SVC is placed at
the regulated bus, it is possible to have a dedicated communica-
tion link between SVC and PMU at low cost. If the calculation
process, application, is integrated with the SVC controller, the
voltage measurement can be treated as a local signal where low
latency could be expected.
The major argument here is that there is a time skew between
the POD signal generated from the four PMU signals and the
voltage measurement since the former still have to pass the
wide-area network and PDC sorting process which inevitably
introduces significantly higher delays compared to the locally
collected measurements. Given the estimation from  that
local PMU measurements are of 10-ms delay while the other
PMU data passing through WAN and PDC sorting are experi-
encing a delay of 47.5 ms, simulations are conducted, and the
results are presented in Fig. 12.
The simulation results reveal that this control design success-
fully damps the oscillation after breaker reclosure even though
a time skew between the POD signal and voltage measurements
exists. It is due to the fact that the POD signal is rather robust to
its measurement delay. Hence, a timely voltage measurement is
an ICT architecture as such, the reliability of this control func-
tion could reach values larger than 99.9999
Fig. 13. Generic ICT architecture for WAMC systems considering the phasor
While the conclusion in terms of ICT requirements can only
be limited to this particular network and wide-area control de-
sign, the results can still raise discussion about the dependency
of the WAMC system on their supporting ICT infrastructure.
Ideally, it is convenient to have unified and integrated common
data processing where all phasor measurements are sorted and
with more stringent requirements in terms of input data, it is
difficult to meet their requirements by implementing one uni-
architecture in response to the particular needs from WAMC
Generally, for the monitoring applications, such as phasor
data set containing global information and sometimes the data
are not collected within one single grid utility’s responsible ter-
ritory. The monitoring applications are intended to assist oper-
ators for decision-making. The participation of operators indi-
cates that there is less stringent constraints on data delay ,
, . On the contrary, the closed-loop control performed
by wide-area control applications, a valid automatic control as
such, in most cases, has to be executed with a time scale of hun-
applications, as such, are, in most cases, performed based on a
subset of theentire phasor data set. In responseto the aforemen-
tioned data delay requirements, a generic two-level hierarchical
architecture enabling PMU-based applications for both control
and monitoring purposes is presented in Fig. 13.
In this architecture, a dedicated PDC or clusters of PDCs are
assigned to each wide-area control application. A distributed
control design, as such, could not only ensure a low commu-
nication delay but mitigate data loss for the monitoring appli-
cations as well. The PDC clusters could also assemble phasor
measurements from the extended portion of networks prior to
forwarding data to centralized locations. Moreover, this design
2808 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 4, OCTOBER 2011 Download full-text
time control on data communication .
VIII. CONCLUSION AND FUTURE WORK
The simulation results in this paper indicate that the sup-
porting ICT system with inappropriate design runs the risk of
invalidating the WAMC systems. To enhance the WAMC sys-
tems’ robustness, besides redesigning the algorithm, optimiza-
tion of the supporting ICT systems could be a feasible alterna-
In the proposed generic architecture, only the data-quality
issues are taken into consideration. However, there are other
nonfunctional aspects of the ICT system that could deteriorate
the quality of service . To control the interconnected power
system in a more responsible manner, it is necessary to ex-
tract data from other systems, even neighboring grid utilities or
other stake holders. The information exchanges occurring be-
yond system or utility boundaries bring in other ICT concerns.
The interface for translation is required to enable communica-
tion between systems whose data are modeled with proprietary
formates while encryption or a firewall need to be setup with
the purpose to secure this communication. The introduction of
these mechanisms runs the risk of slowing down the systems.
It is very interesting to further expand the research to study the
tradeoff between these contradicting ICT entities.
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 M. Chenine,K. Zhu, andL. Nordström,“Survey onpriorities andcom-
munication requirements for pmu-based applications in the nordic re-
gions,” presented at the PowerTech, Bucharest, Romania, 2009.
 A. Phadke and J. Thorp, “Communication needs for wide area mea-
surement applications,” presented at the 5th Int. Conf. Critical Infra-
structures, Beijing, China, Sep. 2010.
 S. Kirti, Z. Wang, A. Scaglione, and R. Thomas, “On the communi-
cation architecture for wide-area real-time monitoring in power net-
Kun Zhu (S’09) received the B.Sc. degree in electric engineering from the
China Agricultural University, Beijing, China, in 2006 and the M.Sc. degree
from the Royal Institute of Technology (KTH), Stockholm, Sweden, in 2008,
where he is currently pursuing the Ph.D. degree.
His research interest lies in the information and communication technology
architecture for smart-grid applications with a particular focus on performance
and data quality.
Moustafa Chenine (S’09) received the B.Sc. degree in computer information
systems from The American College of Greece, Athens, Greece, in 2004 and
the M.Sc. degree in information systems and licentiate of engineering in elec-
trical engineering from the Royal Institute of Technology (KTH), Stockholm,
Sweden, in 2006, where he is currently pursuing the Ph.D. degree in industrial
information and control systems.
He has been conducting research in the field of information and communica-
focusing on interoperability, security, and performance aspects of wide-area
monitoring and control systems.
Lars Nordström (M’05) received the M.Sc. degree in electrical engineering
and the Ph.D. degree in industrial control systems from the Royal Institute of
Technology (KTH), Stockholm, Sweden.
Currently, he is an Associate Professor in Power System Management and
Director of the Swedish Centre of Excellence in Electric Power Engineering,
an industry-university research center, located at KTH. His area of research is
power systems management and related information exchange, including the
application of decision theory on information system architectures and the ap-
plication of ICT to power system problems.
Dr. Nordström is Chairman of IEC TC57’s Swedish committee, and a
member of the IEC’s Strategic group on smart grids as well as the National
CIGRE SC D2 representative for Sweden.