Operation of Graphene Transistors at GHz Frequencies

Abstract

Top-gated graphene transistors operating at high frequencies (GHz) have been fabricated and their characteristics analyzed. The measured intrinsic current gain shows an ideal 1/f frequency dependence, indicating an FET-like behavior for graphene transistors. The cutoff frequency fT is found to be proportional to the dc transconductance gm of the device. The peak fT increases with a reduced gate length, and fT as high as 26 GHz is measured for a graphene transistor with a gate length of 150 nm. The work represents a significant step towards the realization of graphene-based electronics for high-frequency applications.

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Operation of Graphene Transistors at GHz Frequencies
Yu-Ming Lin*, Keith A. Jenkins, Alberto Valdes-Garcia,
Joshua P. Small, Damon B. Farmer, and Phaedon Avouris
Email: yming@us.ibm.com
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
ABSTRACT
Top-gated graphene transistors operating at high frequencies (GHz) have been fabricated and their
characteristics analyzed. The measured intrinsic current gain shows an ideal 1/f frequency
dependence, indicating an FET-like behavior for graphene transistors. The cutoff frequency fT is
found to be proportional to the dc transconductance gm of the device, consistent with the relation
fT=gm/(2πCG). The peak fT increases with a reduced gate length, and fT as high as 26 GHz is
measured for a graphene transistor with a gate length of 150 nm. The work represents a significant
step towards the realization of graphene-based electronics for high-frequency applications.

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Graphene is a two-dimensional (2D) material with great potential for electronics [1, 2]. With
essentially the same lattice structure as an unwrapped carbon nanotube [3], graphene shares
many of the advantages of nanotubes, such as the highest intrinsic carrier mobility at room
temperature of any known materials [4-6]. This makes these carbon-based electronic materials
particularly promising for high-frequency circuits. However, due to the high impedance of a
single carbon nanotube transistor, high-frequency properties of nanotubes were investigated
indirectly using various mixing techniques [7, 8], and direct ac measurements of these devices at
GHz frequencies were realized only recently [9, 10], enabled by the larger device current in
nanotube arrays. In contrast, one distinct advantage of graphene lies in its 2D nature, so that the
drive current of a graphene device, in principle, can be easily scaled up by increasing the device
channel width. This width scaling capability of graphene is of great significance for realizing
high-frequency graphene devices with sufficient drive current for large circuits and associated
measurements. Furthermore, the planar graphene allows for the fabrication of graphene devices
and even integrated circuits utilizing well-established planar processes in the semiconductor
industry. Recently, it was shown that graphene devices can exhibit current gain in the
microwave frequency range [11]. Despite intense activities on graphene research, the intrinsic
high-frequency transport properties of graphene transistors have not been systematically studied.
This letter presents the first comprehensive experimental studies on the high-frequency
response of top-gated graphene transistors for different gate voltages and gate lengths. The
intrinsic current gain of the graphene transistors was found to decrease with increasing frequency
and follows the ideal 1/f dependence expected for conventional FETs. This not only verifies the
ac measurement and de-embedding procedures used here for extracting the intrinsic high-
frequency properties, but also suggests a conventional FET-like behavior for graphene
transistors. The cutoff frequency fT deduced from S parameter measurements exhibits strong

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gate voltage dependence and is proportional to the dc transconductance. The peak cut-off
frequency is found to be inversely proportional to the square of the gate length, and for a gate
length of 150 nm, a peak fT as high as 26 GHz is obtained.
Figure 1 shows the device layout of graphene field-effect transistors with probe pads designed
for high-frequency measurements. Graphene was prepared by mechanical exfoliation on a high-
resistivity Si substrate (>10 kΩ⋅cm) covered by a layer of 300nm thermal SiO2, and Raman
spectroscopy was employed to count the number of graphene layers. The inset of Fig. 1(b)
shows the optical image of a graphene flake, where the region on the left was identified to be
single-layer graphene. Source and drain electrodes made of 1 nm Ti as the adhesion layer and 50
nm-thick Pd were defined by e-beam lithography and lift-off. A 12-nm-thick Al2O3 layer was
then deposited by atomic layer deposition (ALD) at 250ºC as the gate insulator. In order to form
a uniform coating of oxide on graphene, a functionalization layer consisting of 50 cycles of NO2-
TMA (trimethylaluminum) was first deposited prior to the growth of gate oxide [12, 13]. This
NO2-TMA functionalization layer was essential for the ALD process to achieve thin (<10 nm)
gate dielectrics on graphene without producing pinholes that cause gate leakage. The dielectric
constant of ALD-grown Al2O3 is determined by C-V measurements and found to be about 7.5.
Lastly, 10nm/50nm Pd/Au was deposited and patterned to form the top gate. As shown in Fig.
1(b), the source electrodes were designed to overlap the entire graphene flake (see figure inset)
in order to minimize the uncertainty in the de-embedding process for high-frequency S-
parameter measurements, as explained below. In the device shown in Fig. 1(b), the distance
between the source and drain electrodes is 500 nm, and the top gate underlaps the source-drain
gap with a gate length LG of 360 nm. The total gate width (or channel width), including both
channels, is ~ 40µm. Fig. 1(a) shows the optical image of the complete device layout where the

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standard ground-signal-ground probing pads are realized for the gate and the drain to allow for
transition from coax to on-chip coplanar waveguide (CPW) electrodes.
Measurements of dc electrical properties of graphene devices were performed in order to gain
insight into their high-frequency response. In addition, the dc electrical characteristics were
monitored at each fabrication step so that issues affecting the final device performance could be
identified. Fig. 2 shows the conductance, G = ID/VD, of a graphene device before ALD oxide
deposition, using the Si substrate as the back gate and a dc source-drain bias VD of 100 mV. The
field-effect mobility µeff can be calculated using the relation ∆σ = q ∆n µeff , where n is the 2D
carrier density that is controlled by the gate voltage. For this as-prepared graphene device, µeff is
estimated to be 400 cm2/V⋅s. After the deposition of top gate dielectrics by ALD, there was
significant reduction in both the device conductance and field-effect mobility (see inset of Fig.
2)). The current and mobility degradation in the oxide-covered devices may be attributed to
charged impurity scattering associated with the NO2 functionalization layer and interface phonon
scattering in the oxide [4]. Similar impact of the oxide environment on electrical properties of
graphene was previously observed [14, 15], and these results indicate that further oxide
optimization or alternative dielectrics are required in order to benefit from the high intrinsic
mobilities in graphene.
The dc electrical characteristics of the completed graphene device after the deposition of the
top-gate electrode are shown in Fig. 3(a). The inset shows the measured current as a function of
(top-gate) voltage VG at a drain bias of VD = 100 mV. Despite the small on/off ratio, the
graphene devices are essentially ambipolar field-effect transistors, as indicated by the "V"-shape
gate dependence in the measured ID-VG curve. In these graphene field-effect transistors (GFET),
the transport is dominated by electrons and holes for positive and negative gate voltages,
respectively, and the conductance minimum is denoted as the Dirac point where electrons and

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holes make equal contributions to the transport. Compared with the inset of Fig. 2 for the back-
gated device, the top-gated GFET exhibits no discernible changes in minimum conductance or
the on-current, indicating that metallization of top-gate electrodes did not alter the properties of
graphene channel. Fig. 3(a) shows the n-type output characteristics, ID-VD, of the graphene
transistor at various gate voltages. It is found that the top-gated GFETs studied here exhibit a
nearly linear ID-VD dependence up to 1.6 V for the gate voltage ranges measured. This lack of
current saturation is due to the fact that graphene is a zero-gap semiconductor. It has been
suggested that velocity saturation at higher biases may lead to the current saturation phenomenon
in graphene transistors [16]. However, a higher carrier mobility may be required to achieve this
saturation velocity within the drain bias of practical interest.
The high-frequency performance of a transistor for small-signal response is mainly determined
by the transconductance gm = dID/dVG. Fig. 3(b) shows the measured transconductance of the
GFET as a function of gate voltage VG for different drain biases. Both the sign and magnitude of
gm are found to be strongly dependent on the gate voltage. The negative gm branch represents p-
type transport dominated by holes, and gm changes sign with increasing gate voltage as the
channel becomes n type. For both branches, the magnitude of gm rises with increasing VD
because the graphene transistor possesses nearly linear ID-VD output characteristics in this
operation regime. At VD = 1.6 V, the peak gm values are ~45 mS/mm and -35mS/mm for n and p
branches, respectively, in this 360-nm-gate device.
To probe the high-frequency response of the GFET, on-chip microwave measurements were
carried out using a HP8510 vector network analyzer up to 10 GHz to obtain the scattering S-
parameters that relate the ac currents and voltages between the drain and the gate of the GFET.
A standard open, short and load calibration was employed to calibrate the network analyzer, and
short and open structures were used to de-embed the signals of the parasitic capacitance and the