Conference Paper

FPGA Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and Performance Comparison for Multiple Error Correction Control

DOI: 10.1109/CSNT.2012.170 Conference: IEEE International Conference on Communication Systems and Network Technologies, Volume: 2

ABSTRACT In this paper we have designed and implemented (15, k) a BCH Encoder on FPGA using VHDL for reliable data transfer in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (2 4) with irreducible primitive polynomial x 4 +x+1 is organised into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form upto k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 codeword. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 10.1. Also a comparative performance based on synthesis & simulation on FPGA is presented.

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    Proceedings of the IEEE 10/1986; · 5.47 Impact Factor
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    ABSTRACT: In fact “both students and practicing engineers will benefit from the information in this self-contained survey of error control. Current and complete with biographical references, it can serve as a starting point for those conducting graduate-level work in error control coding. As an applications-oriented text, it provides the background necessary to design and implement error control subsystems for digital communication systems. Finally, it includes a tutorial on trellis coded modulation and an up-to-date treatment of ARQ protocols. Containing four basic parts (Finite field theory, Block codes, Convolutional/trellis codes, and System design), Error control systems for digital communication and storage: – Provides an introduction to Galois fields and polynomials with coefficients over Galois fields (Chapters 2-3). – Covers the various types of block error control codes that are currently being used or show promise of use in the future, including BCH and Reed-Solomon (Chapters 4-9). – Treats convolutional codes and their trellis coded progeny; presents the design and performance of the Viterbi and sequential decoding algorithms; discusses the design and use of rate compatible punctured convolutional codes; and offers chapter-length treatment of trellis codes (Chapters 11-14). – Discusses the various means for analyzing the performance of block codes over a variety of channels, particularly the slowly fading channel; examines retransmission request systems that make use of the various block, convolutional, and trellis codes; and explores some specific design applications, including the Compact Disc TM player and the magnetic recording channel (Chapters 1, 10, 15-16)” (from the cover). In addition the five helpful appendices have to be mentioned which list e.g. binary primitive polynomials, add-one tables and vector-space representations for Galois fields of size 2 m , cyclotomic cosets modulo 2 m -1, minimal polynomials of elements in GF(2 m ) and generator polynomials of binary BCH codes.


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May 29, 2014