Conference Paper

# FPGA Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and Performance Comparison for Multiple Error Correction Control

DOI: 10.1109/CSNT.2012.170 Conference: IEEE International Conference on Communication Systems and Network Technologies, Volume: 2

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**ABSTRACT:**A feedback-with-carry shift register (FCSR) with "Fibonacci" architecture is a shift register provided with a small amount of memory which is used in the feedback algorithm. Like the linear feedback shift register (LFSR), the FCSR provides a simple and predictable method for the fast generation of pseudorandom sequences with good statistical properties and large periods. In this paper, we describe and analyze an alternative architecture for the FCSR which is similar to the "Galois" architecture for the LFSR. The Galois architecture is more efficient than the Fibonacci architecture because the feedback computations are performed in parallel. We also describe the output sequences generated by the d-FCSR, a slight modification of the (Fibonacci) FCSR architecture in which the feedback bit is delayed for d clock cycles before being returned to the first cell of the shift register. We explain how these devices may be configured so as to generate sequences with large periods. We show that the d-FCSR also admits a more efficient "Galois" architectureIEEE Transactions on Information Theory 12/2002; · 2.62 Impact Factor - [Show abstract] [Hide abstract]

**ABSTRACT:**The main purpose of this paper is to study the FPGA implementation and performance analysis of 8, 16, and32 bit LFSR pseudo random number generator system. We have used FPGA to explain how FPGA's ease the hardware implementation part of communication systems. The analysis is conceded out to find number of gates, memory and speed requirement in FPGA as the number of bits is increased. The comparative study of 8, 16 and 32 bit LFSR on FPGA is shown here to understand the on chip verification. Recently the field programmable gate arrays have enjoyed wide spread use due to several advantages related to relatively high gate density, short design cycle and low cost. The greatest advantage of FPGA's are flexibility that we reconfigured the design many times and check the results and verify it on-chip for comparing with others PN sequence generators. The logic of PN Sequence Generator presented here can be changed any time, if we want a PN generator of more length all we need to do is change the number of shift register and adjust the taps. In this paper we have used one XOR operation for taping. Also we can use XNOR operation for taping. By increasing the number of tapping we can generate more randomness in the sequence.03/2012; 3:2231-1963. - [Show abstract] [Hide abstract]

**ABSTRACT:**Not AvailableIEEE Communications Magazine 05/1987; 25(4):44- 57. · 3.66 Impact Factor

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