ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell
ABSTRACT For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 μA/μm at Ioff = 100 nA/μm for high performance (HP) and 920/880 μA/μm at Ioff = 1 nA/μm for low power (LP), respectively, at VDD = 1 V. High density 6-T SRAM cells down to 0.08 μm2 are demonstrated. Compared with a 28nm bulk LP technology, the high drive currents of ETSOI transistors coupled with large capacitance reduction by aggressive LG scaling result in 25% improvement in ETSOI ring oscillator (RO) speed. Auxiliary ETSOI devices including epitaxy resistors with high precision and gated diodes with near ideal characteristics are fabricated to complete device menu for early ETSOI SoC design.
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ABSTRACT: In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations.IEEE Transactions on Electron Devices 05/2012; 59(5):1332-1344. DOI:10.1109/TED.2012.2187454 · 2.36 Impact Factor