One of the most serious issues in information industries is the bandwidth bottleneck in inter-chip interconnects. We propose a photonics-electronics convergence system to solve this issue. We fabricated a high density optical interposer to demonstrate the feasibility of the system by using silicon photonics integrated with an arrayed laser diode, an optical splitter, silicon optical modulators, germanium photodetectors, and silicon optical waveguides on a single silicon substrate. Error-free data transmission at 12.5 Gbps and a transmission density of 6.6 Tbps/cm2 were achieved with the optical interposer. We believe this technology will solve the bandwidth bottleneck problem in the future.
"Current development efforts are focused on using lasers made of III–V semiconductors. The lasers can be coupled to the silicon PICs by flip-chip bonding techniques at the die level . A wafer level approach by bonding the III–V wafer at selective areas on the SOI substrate and then proceeding with laser fabrication has also been demonstrated by a number of groups , , . "
[Show abstract][Hide abstract] ABSTRACT: The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes. In particular, for several established research and development foundries that grant general access, silicon-on-insulator wafers with a silicon thickness of 220 nm have become the standard substrate for which devices and circuits have to be designed. In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration. We find that in all devices considered there is an advantage in using a silicon thickness larger than 220 nm, either for improved performance or for simplified fabrication processes and relaxed tolerances.
IEEE Journal of Selected Topics in Quantum Electronics 07/2014; 20(4):189-205. DOI:10.1109/JSTQE.2014.2299634 · 2.83 Impact Factor
"We are investigating a Si optical interposer that integrates optical modulators, PDs, and QD LDs, and, given the loss budget that has been obtained at present , have confirmed that the light power introduced into a Si waveguide is high enough to achieve an optical link at temperatures up to 85 • C. Fig. 13 "
[Show abstract][Hide abstract] ABSTRACT: This paper reports a hybrid integrated light source fabricated on a Si platform using a spot-size converter (SSC) with a trident Si waveguide. Low-loss coupling for 1.55 μm and 1.3 μm wavelengths was achieved with merely the simple planar form of a Si waveguide with no use of complicated structures such as vertical tapers or an extra dielectric core overlaid on the waveguide. The coupling loss tolerance up to a 1 dB loss increase was larger than the accuracy of our passive alignment technology. The coupling efficiency was quite robust against manufacturing variations in the waveguide width compared with that of a conventional SSC with an inverse taper waveguide. A multi-channel light source with highly uniform output power and a high-temperature light source were fabricated with a 1.55 μm quantum well laser and a 1.3 μm quantum dot laser, respectively. The integration scheme we report can be used to fabricate light sources for high-density, multi-channel Si optical interposers.
"Si photonics has been intensively researched and developed as it provides a low-cost and power efficient solution for next generation interconnect technology based on on-chip, chip-to-chip, and long-haul optical communication –. A multifunctional platform requires photonics and complementary metal–oxide–semiconductor (CMOS) circuits to be integrated in a same system. "
[Show abstract][Hide abstract] ABSTRACT: Si photonic devices are sensitive to the change in refractive index on the Si-on-insulator (SOI) platform. One of the critical limitations in the compact 3D photonic integration circuit is the through-Si-via (TSV)-induced stress, which affects the performances of Si photonic devices integrated in interposer. We build a model to analyze and simulate the wavelength shift of the ring resonator caused by the effective-refractive-index change in the waveguide, arising from TSV-induced stress in the SOI interposer. Double-cascaded ring resonators integrated in the SOI interposer were fabricated and their wavelength shifts were characterized. The results show that the resonance wavelength shift on the order of 0.1 nm can be caused by the TSV-induced stress for , where d and R are the distance between the TSV and the Si waveguide, and the radius of TSV, respectively. This shift results in performance deviation from the target of design. Finally, this paper proposes a TSV keep-out-zone for the Si photonic ring resonator and a compact scaling of the SOI photonics interposer.
Data provided are for informational purposes only. Although carefully collected, accuracy cannot be guaranteed. The impact factor represents a rough estimation of the journal's impact factor and does not reflect the actual current impact factor. Publisher conditions are provided by RoMEO. Differing provisions from the publisher's actual policy or licence agreement may be applicable.