Conference Paper

Benchmarking and Improving III-V Esaki Diode Performance with a Record 2.2 MA/cm2 Peak Current Density to Enhance TFET Drive Current

DOI: 10.1109/IEDM.2012.6479118 Conference: International Electron Device Meeting


Recently, III-V tunneling field effect transistors (TFET) for low voltage logic applications (<0.5V) have gained attention with the demonstration of sub-60 mV/dec. subthreshold slopes [1]. A key outstanding issue with TFETs is limited drive currents, due to non-optimized carrier tunneling. With that issue in mind, the aim of this work is to map III-V Esaki tunnel diode (TD) performance to engineer TDs with ultra high current densities while maintaining large peak-to-valley current ratios (PVCR). This work describes the most comprehensive experimental benchmarking of TD performance reported, including (i) GaAs, (ii) In0.53Ga0.47As, (iii) InAs, (iv) InAs 0.9Sb0.1/Al0.4Ga0.6Sb, and (v) InAs/GaSb as a function of doping and effective tunnel barrier height. These results confirm that heterojunctions (bandgap engineering) and doping will enhance peak (JP) and Zener current densities beyond homojunction TDs [3], to a record 2.2MA/cm2 (JP) and 11 MA/cm2 (@ -0.3 V), laying the fundamental groundwork for a III-V TFET at the 7 nm technology node.

Download full-text


Available from: Sean Rommel, Oct 03, 2015
76 Reads
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: With voltage scaling to reduce power consumption in scaled transistors the subthreshold swing is becoming a critical factor influencing the minimum voltage margin between the transistor on and off-states. Conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamentally limited to a 60 mV/dec swing due to the thermionic emission current transport mechanism at room temperature. Tunnel field-effect transistors (TFETs) utilize band-to-band tunneling as the current transport mechanism resulting in the potential for sub-60 mV/dec subthreshold swings and have been identified as a possible replacement to the MOSFET for low-voltage logic applications. The TFET operates as a gated p-i-n diode under reverse bias where the gate electrode is placed over the intrinsic channel allowing for modulation of the tunnel barrier thickness. When the barrier is sufficiently thin the tunneling probability increases enough to allow for significant number of electrons to tunnel from the source into the channel. To date, experimental TFET reports using III-V semiconductors have failed to produce devices that combine a steep subthreshold swing with a large enough drive current to compete with scaled CMOS. This study developed the foundations for TFET fabrication by improving an established Esaki tunnel diode process flow and extending it to include the addition of a gate electrode to form a TFET. The gating process was developed using an In 0.53 Ga 0.57 As TFET which demonstrated a minimum subthreshold slope of 100 mV/dec. To address the issue of TFET drive current an InAs/GaSb heterojunction TFET structure was investigated taking advantage of the smaller tunnel barrier height.
    08/2013, Degree: M.S. Microelectronic Engineering, Supervisor: Sean L. Rommel
  • [Show abstract] [Hide abstract]
    ABSTRACT: We report a theoretical investigation on the electrical properties of a Sn-based group-IV structure for a resonant tunneling diode (RTD). The analysis on the composition-dependent strain, energy profile, and current-voltage characteristic of a double-barrier heterostructure shows that the peak current density and peak-to-valley ratio are enhanced with a moderated tensile strain in the barrier layer, providing an alternative approach for group-IV RTDs.
    IEEE Electron Device Letters 08/2013; 34(8):951-953. DOI:10.1109/LED.2013.2266540 · 2.75 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: In the �field of low power electronics, Tunnel �field-e�ffect transistors (TFETs) are gaining momentum due to aggressive voltage scaling. To enable scaling of power supply while maintaining a high Ion, a steep subthreshold slope and low I0 are required. A TFET operates as a gated PIN diode under reverse bias with the intrinsic region as the channel. This study focuses on minimizing I0 in a III-V homojunction PIN diode. I0 or leakage current is the current flowing in a PIN diode under reverse bias, that forms the off�-state current (Vgate = 0 V) in a TFET.
    05/2015, Degree: Master of Science in Microelectronic Engineering, Supervisor: Sean L. Rommel