Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy
ABSTRACT In this paper, BISR (built-in self-repair) techniques with hierarchical redundancy architecture are proposed for word-oriented embedded memories. Our BISR circuit consists of a built-in self-test (BIST) module and a built-in redundancy-analysis (BIRA) module. Spare words, spare rows, and spare columns are added into the memory cores as redundancy. However, the spare rows and spare columns are virtually divided into spare row blocks and spare column group blocks. The address reconfiguration is performed at row block or column group block level instead of the traditional row or column level. An extended essential spare pivoting (EESP) algorithm is proposed for redundancy analysis based on the proposed redundancy organization. A practical 16K .. 32 SRAM with BISR circuitry is designed and implemented. Experimental results show that we can obtain a higher repair rate with negligible area overhead (2.56%) of the BISR circuit for a 1024K .. 2048-bit SRAM chip.
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ABSTRACT: As RAM is major component in present day SOC, by improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip. This paper presents the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit along with 2D redundancies (spare row/column) and spare cells. Since most of faults are single cell fault, the area of spare is effectively utilized by replacing defected cell with spare cell. This in turn increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. The experimental results show that proposed ReBISR circuit reduces the area and increases the yield of the memory.International Journal of Computer Applications 06/2011; 24(8). DOI:10.5120/2971-3995 · 0.82 Impact Factor
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ABSTRACT: With the growth of memory capacity and density, test cost and yield improvement are becoming more important. In the case of embedded memories for systems-on-a-chip (SOC), built-in redundancy analysis (BIRA) is widely used as a solution to solve quality and yield issues by replacing faulty cells with extra good cells. However, previous BIRA approaches focused mainly on embedded memories rather than commodity memories. Many BIRA approaches require extra hardware overhead to achieve the optimal repair rate, which means that 100% of solution detection is guaranteed for intrinsically repairable dies, or they suffer a loss of repair rate to minimize the hardware overhead. In order to achieve both low area overhead and optimal repair rate, a novel BIRA approach is proposed and it builds a line-based searching tree. The proposed BIRA minimizes the storage capacity requirements to store faulty address information by dropping all unnecessary faulty addresses for inherently repairable die. The proposed BIRA analyzes redundancies quickly and efficiently with optimal repair rate by using a selected fail count comparison algorithm. Experimental results show that the proposed BIRA achieves optimal repair rate, fast analysis speed, and nearly optimal repair solutions with a relatively small area overhead.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12/2009; 17:1665-1678. DOI:10.1109/TVLSI.2008.2005988 · 1.14 Impact Factor
Conference Paper: An Advanced BIRA Using Parallel Sub-analyzers for Embedded Memories[Show abstract] [Hide abstract]
ABSTRACT: Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed.SoC Design Conference (ISOCC), 2009 International; 12/2009