Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy
ABSTRACT In this paper, BISR (built-in self-repair) techniques with hierarchical redundancy architecture are proposed for word-oriented embedded memories. Our BISR circuit consists of a built-in self-test (BIST) module and a built-in redundancy-analysis (BIRA) module. Spare words, spare rows, and spare columns are added into the memory cores as redundancy. However, the spare rows and spare columns are virtually divided into spare row blocks and spare column group blocks. The address reconfiguration is performed at row block or column group block level instead of the traditional row or column level. An extended essential spare pivoting (EESP) algorithm is proposed for redundancy analysis based on the proposed redundancy organization. A practical 16K .. 32 SRAM with BISR circuitry is designed and implemented. Experimental results show that we can obtain a higher repair rate with negligible area overhead (2.56%) of the BISR circuit for a 1024K .. 2048-bit SRAM chip.
- [show abstract] [hide abstract]
ABSTRACT: Yield degradation from physical failures in large memories and processor arrays is of significant concern to semiconductor manufacturers. One method of increasing the yield for iterated arrays of memory cells or processing elements is to incorporate spare rows and columns in the die or wafer. These spare rows and columns can then be programmed into the array. The authors discuss the use of CAD approaches to reconfigure such arrays. The complexity of optimal reconfiguration is shown to be NP-complete. The authors present two algorithms for spare allocation that are based on graph-theoretic analysis. The first uses a branch-and-bound approach with early screening based on bipartite graph matching. The second is an efficient polynomial time-approximation algorithm. In contrast to existing greedy and exhaustive search algorithms, these algorithms provide highly efficient and flexible reconfiguration analysis.IEEE Design and Test of Computers 03/1987; · 1.62 Impact Factor
Conference Proceeding: Novel fault-tolerant techniques for high capacity RAMs[show abstract] [hide abstract]
ABSTRACT: In the area of high capacity RAMs, the memory columns (rows), including the redundancies, are partitioned into column blocks (row blocks), respectively. If the replacement is performed at the row-block level, then a row block-based FTM (RBFTM) system is used. Alternatively, if the replacement is performed at the column-block level, then a column block-based FTM (CBFTM) system is used. If both approaches are incorporated into a memory chip, then the hybrid FTM (HFTM) system is achieved. Experimental results and analysis show that our fault-tolerant architectures can improve the yield for memory fabrication significantly. The reconfiguration mechanism requires almost negligible hardware overhead for high capacity memories. Moreover, the repair rates among different fault-tolerant strategies are also comparedDependable Computing, 2001. Proceedings. 2001 Pacific Rim International Symposium on; 02/2001
- [show abstract] [hide abstract]
ABSTRACT: Two approaches for the repair of large random access memory (RAM) devices in which redundant rows and columns are added as spares are presented. These devices, referred to as redundant RAMs, are repaired to achieve acceptable yield at manufacturing and production times. The first approach, the faulty line covering technique, is a refinement of the fault-driven approach. This approach finds the optimal repair solution within a smaller number of iterations than the fault-driven algorithm. The second approach exploits a heuristic criterion in the generation of the repair solution. This heuristic criterion permits a fast repair. The criterion is based on the calculation of efficient coefficients for the rows and columns of the memory. Simulation results are presented. Comparison of the proposed heuristic approaches with the fully exhaustive approach shows that repair can be accomplished in most cases. A considerable reduction in processing and complexity (number of records generated in the repair process for finding the optimal repair solution) is accomplishedIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 04/1990; · 1.09 Impact Factor