Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy

Computer and Information Science, 5th IEEE/ACIS International Conference on 01/2006; DOI: 10.1109/ICIS-COMSAR.2006.32

ABSTRACT In this paper, BISR (built-in self-repair) techniques with hierarchical redundancy architecture are proposed for word-oriented embedded memories. Our BISR circuit consists of a built-in self-test (BIST) module and a built-in redundancy-analysis (BIRA) module. Spare words, spare rows, and spare columns are added into the memory cores as redundancy. However, the spare rows and spare columns are virtually divided into spare row blocks and spare column group blocks. The address reconfiguration is performed at row block or column group block level instead of the traditional row or column level. An extended essential spare pivoting (EESP) algorithm is proposed for redundancy analysis based on the proposed redundancy organization. A practical 16K .. 32 SRAM with BISR circuitry is designed and implemented. Experimental results show that we can obtain a higher repair rate with negligible area overhead (2.56%) of the BISR circuit for a 1024K .. 2048-bit SRAM chip.

  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: As memory capacity and density grow, a corresponding increase in the number of defects decreases the yield and quality of embedded memories for systems-on-chip as well as commodity memories. For embedded memories, built-in redundancy analysis (BIRA) is widely used to solve quality and yield issues by replacing faulty cells with healthy redundant cells. Many BIRA approaches require extra hardware overhead in order to achieve optimal repair rates, or they suffer a loss of repair rate in minimizing the hardware overhead. An innovative BIRA approach is proposed to achieve optimal repair rates, lower area overhead, and increase analysis speed. The proposed BIRA minimizes area overhead by eliminating some storage coverage for only must-repair faulty information. The proposed BIRA analyzes redundancies quickly and efficiently by evaluating all nodes of a branch in parallel with a new analyzer which is simple and easy-to-implement. Experimental results show that the proposed BIRA allows for a much faster analysis speed than that of the state-of-the-art BIRA, as well as the optimal repair rate, and relatively small area overhead.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/2011; · 1.09 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy for embedded memories. This paper proposes an efficient BISR strategy which consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible that it can provide four operation modes to SRAM users. Each fault address can be saved only once is the feature of the proposed BISR strategy. In BIAA module, fault addresses and redundant ones form a one-to-one mapping to achieve a high repair speed. Besides, instead of adding spare words, rows, columns or blocks in the SRAMs, users can select normal words as redundancy. The selectable redundancy brings no penalty of area and complexity and is suitable for compiler design. A practical 4K × 32 SRAM IP with BISR circuitry is designed and implemented based on a 55nm CMOS process. Experimental results show that the BISR occupies 20% area and can work at up to 150MHz.
  • [Show abstract] [Hide abstract]
    ABSTRACT: In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a set of direct-mapped cache banks to replace faulty words. Statistical and mathematical probability analysis shows that the proposed scheme achieves high repairability levels with low area and static power dissipation overheads, the latter being a dominant issue in nanometer technologies. It is therefore a suitable solution along with other mature memory repair techniques, to enhance the overall repairability features and guarantee the correct and reliable operation of embedded memories in nanometer technologies.
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems 01/2012; 20(12):2278-2288. · 1.22 Impact Factor