Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy
ABSTRACT In this paper, BISR (built-in self-repair) techniques with hierarchical redundancy architecture are proposed for word-oriented embedded memories. Our BISR circuit consists of a built-in self-test (BIST) module and a built-in redundancy-analysis (BIRA) module. Spare words, spare rows, and spare columns are added into the memory cores as redundancy. However, the spare rows and spare columns are virtually divided into spare row blocks and spare column group blocks. The address reconfiguration is performed at row block or column group block level instead of the traditional row or column level. An extended essential spare pivoting (EESP) algorithm is proposed for redundancy analysis based on the proposed redundancy organization. A practical 16K .. 32 SRAM with BISR circuitry is designed and implemented. Experimental results show that we can obtain a higher repair rate with negligible area overhead (2.56%) of the BISR circuit for a 1024K .. 2048-bit SRAM chip.
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ABSTRACT: As RAM is major component in present day SOC, by improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip. This paper presents the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit along with 2D redundancies (spare row/column) and spare cells. Since most of faults are single cell fault, the area of spare is effectively utilized by replacing defected cell with spare cell. This in turn increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. The experimental results show that proposed ReBISR circuit reduces the area and increases the yield of the memory.International Journal of Computer Applications 06/2011; 24(8). DOI:10.5120/2971-3995 · 0.82 Impact Factor
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ABSTRACT: In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a set of direct-mapped cache banks to replace faulty words. Statistical and mathematical probability analysis shows that the proposed scheme achieves high repairability levels with low area and static power dissipation overheads, the latter being a dominant issue in nanometer technologies. It is therefore a suitable solution along with other mature memory repair techniques, to enhance the overall repairability features and guarantee the correct and reliable operation of embedded memories in nanometer technologies.IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12/2012; 20(12):2278-2288. DOI:10.1109/TVLSI.2011.2170593 · 1.14 Impact Factor
Conference Paper: Modeling of redundancy analyzer in BISR for RAM[Show abstract] [Hide abstract]
ABSTRACT: In the current SoC implementation embedded memories are most widely used cores. They usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Embedded memories have become very vulnerable to even minor process variations, resulting in low manufacturing yield & reliability. Efficient yield-enhancement techniques for embedded memories are thus important for SoC. The Built in Self Repair (BISR) includes two modules Built in Self Test (BIST) and Built-In Redundancy Analysis (BIRA). The BIRA circuit performs the redundancy allocation using the proposed RA algorithm. The purpose of RA is to allocate appropriate redundant (spare) memory elements to replace the defective cells, such that the utilization of the spare elements can be optimized. In a memory with BISR, the RA collects the fault information from the BIST. RA performs the analysis after the fault bit-map of a defective memory is constructed. In this paper, it is proposed to model a RA technique for a 2D Random Access Memory of 512 bit with spare rows and columns. This Analyzer decides which spare element to be allocated for a fault adaptively by considering the fault count on each row/column. The model is simulated using Aldec Active HDL version 6.3 and synthesised using Xilinx ISE tool 9.1.2013 IEEE Postgraduate Research in Microelectronics and Electronics Asia (PrimeAsia); 12/2013