A Family of Parallel-Pre.x Modulo 2n - 1 Adders

Dept. of Comput. Eng. & Informatics, Patras Univ., Greece
International Conference on Application-Specific Systems, Architectures and Processors, Proceedings 07/2003; DOI: 10.1109/ASAP.2003.1212856
Source: IEEE Xplore

ABSTRACT In this paper we at .rst reveal the cyclic nature of idempotency in the case of modulo 2n - 1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2n- 1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.

1 Bookmark
  • [Show abstract] [Hide abstract]
    ABSTRACT: Two architectures for modulo 2<sup>n</sup>+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2<sup>n</sup>+1 addition. This sparse approach is enabled by the introduction of the inverted circular idempotency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed. The second architecture unifies the design of modulo 2<sup>n</sup> ± 1 adders. It is shown that modulo 2<sup>n</sup>+1 adders can be easily derived by straightforward modifications of modulo 2<sup>n</sup>-1 adders with minor hardware overhead.
    IEEE Transactions on Computers 03/2012; · 1.47 Impact Factor
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The need for efficient implementation of simple crossbar schedulers has increased in the recent years due to the advent of on-chip interconnection networks that require low latency message delivery. The core function of any crossbar scheduler is arbitration that resolves conflicting requests for the same output. Since, the delay of the arbiters directly determine the operation speed of the scheduler, the design of faster arbiters is of paramount importance. In this paper, we present a new bit-level algorithm and new circuit techniques for the design of programmable priority arbiters that offer significantly more efficient implementations compared to already-known solutions. From the experimental results it is derived that the proposed circuits are more than 15% faster than the most efficient previous implementations, which under equal delay comparisons, translates to 40% less energy.
    Computer Design, 2008. ICCD 2008. IEEE International Conference on; 11/2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: Numerous architectures have been recently proposed for residue arithmetic components, each with its own speed, area and power consumption characteristics. In this paper, we present KoVer, a novel software tool that gives a designer the opportunity to explore several architectures for implementing his residue arithmetic blocks, select the one that best suits his goals and instantly get the HDL level description of the selected architecture.
    Rapid System Prototyping, 2005. (RSP 2005). The 16th IEEE International Workshop on; 07/2005


Available from