A Family of Parallel-Pre.x Modulo 2n - 1 Adders

Dept. of Comput. Eng. & Informatics, Patras Univ., Greece
International Conference on Application-Specific Systems, Architectures and Processors, Proceedings 07/2003; DOI: 10.1109/ASAP.2003.1212856
Source: IEEE Xplore

ABSTRACT In this paper we at .rst reveal the cyclic nature of idempotency in the case of modulo 2n - 1 addition. Then based on this property, we derive for each n, a family of minimum logic depth modulo 2n- 1 adders, which allows several trade-offs between the number of operators, the internal wire length, and the fanout of internal nodes. Performance data, gathered using static CMOS implementations, reveal that the proposed architectures outperform all previously reported ones in terms of area and/or operation speed.

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