Fabrication of epitaxial CoSi nanowires

Applied Physics Letters (Impact Factor: 3.3). 12/2000; 79(6):824. DOI: 10.1063/1.1390318


We have developed a method for fabricating epitaxial CoSi2 nanowires using only conventional optical lithography and standard silicon processing steps. This method was successfully applied to ultrathin epitaxial CoSi2 layers grown on Si(100) and silicon-on-insulator substrates. A nitride mask induces a stress field near its edges into the CoSi2/Si heterostructure and leads to the separation of the CoSi2 layer in this region during a rapid thermal oxidation step. A subsequent etching step and a second oxidation generate highly homogenous silicide wires with dimensions down to 50 nm. (C) 2001 American Institute of Physics.

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Available from: Qing-Tai Zhao, Oct 04, 2015
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    ABSTRACT: CoSi -nanostructures were fabricated using a self-assembly process involving local oxidation of silicides 2 (LOCOSI). The nanostructures are generated along the edge of a mask consisting of SiO and Si N , deposited 2 3 4 by plasma enhanced chemical vapor deposition (PECVD) and patterned with conventional optical lithography. The mask induces a stress field near its edges into the underlying CoSi / Si-heterostructure. Rapid thermal 2 oxidation (RTO) leads to the separation of the CoSi layer in this region due to the concomitant anisotropic 2 diffusion of the cobalt atoms in the stress field. Using this method, uniform gaps and narrow wires were produced from 20–30 nm-thick single-crystalline, epitaxial CoSi -layers grown by molecular beam allotaxy 2 (MBA) on conventional Si(100) and silicon-on-insulator (SOI) substrates. These structures with dimensions down to 40 nm can be used as building blocks for nanoscale metal-oxide-semiconductor field effect transistor (MOSFET) devices. We produced 70 nm gate-length Schottky barrier MOSFETs (SBMOSFETs) on SOI using the silicide nanostructures. These devices can be driven as both p-channel and n-channel MOSFETs without complementary substrate doping and show good I–V characteristics.  2002 Elsevier Science B. V. All rights reserved.
    Microelectronic Engineering 10/2002; 64(1):163-171. DOI:10.1016/S0167-9317(02)00781-5 · 1.20 Impact Factor
  • Advanced Materials 04/2003; 15(7‐8):579 - 581. DOI:10.1002/adma.200304432 · 17.49 Impact Factor
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    ABSTRACT: A patterning method for the generation of epitaxial CoSi 2 nanostructures was developed based on anisotropic diffusion of Co/ Si atoms in a stress field during rapid thermal oxidation (RTO). The stress field is generated along the edge of a mask consisting of a thin SiO 2 layer and a Si 3 N 4 layer. During RTO of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. The technique was used to make 50-nm channel-length metal-oxide-semiconductor field-effect transistors (MOSFETs). These highly uniform gaps define the channel region of the fabricated device. Two types of MOSFETs have been fabricated: symmetric transistor structures, using the separated silicide layers as Schottky source and drain, and asymmetric transistors, with n + source and Schottky drain. The asymmetric transistors were fabricated by an ion implantation into the unprotected CoSi 2 layer and a subsequent out diffusion to form the n + source. The detailed fabrication process as well as the I – V characteristics of both the symmetric and asymmetric transistor structures will be presented. © 2004 American Institute of Physics. [
    Journal of Applied Physics 11/2004; 96(10):5775. DOI:10.1063/1.1808246 · 2.18 Impact Factor
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