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Development of a tungsten plasma etch process for IR nanobolometer fabrication
Abstract
In this paper we present our development of a SF6/Cl2-based plasma etch recipe for a LAM Research 4720 etch chamber. Our tungsten plasma etch recipe is used to pattern nanoscale resistor features integrated within a novel IR sensor process. We characterised the nanoscale etch in terms of five primary process parameters using a 16-run V fractional factorial experiment, to provide accurate estimates of all main effects and two-factor interactions. The experimental results determined the target levels for the etch process parameters. Our optimised nanoscale tungsten etch module was then integrated within a CMOS/MEMs-compatible nanobolometer infrared (IR) sensor fabrication flow. Our use of tungsten improves the reliability of the sensor pixels at elevated stress current levels, when compared with equivalent Ti-based pixel structures, and demonstrates the potential of tungsten as a CMOS-compatible nanobolometer material.
Y3Al5O12 (YAG), Y2O3 and Al2O3 ceramic coatings were manufactured to investigate the plasma erosion properties. The X‐Ray Diffraction (XRD) analysis confirmed that YAG coating was synthesized successfully by Y2O3 and Al2O3 mixture suspension using the plasma spraying method. Meanwhile, metastable phases were found in Y2O3 and Al2O3 coatings due to the quenching in cooling process of melted droplets. The coating surface morphology and microstructure of cross sections were characterized by SEM. The results reveal that coatings are composed by ultrafine splats and exhibit dense lamellar structure. The plasma erosion properties were evaluated at different etching test power under Ar/CF4/O2 plasma gas. The experimental results clarify that both of YAG and Y2O3 coatings show the better plasma erosion resistance than Al2O3 coatings. The formation of fluorination layer surface prevents the coatings from further erosion with plasma gas. Moreover, the etching rate of coatings depended on the fluorination and removing rate of fluoride layer.
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The review considers plasma-processing technologies used in solid-state electronics, both widely used and ones, which do not found yet industrial applications. Several from them are developed specifically for creating nanoelectronic devices. Tendencies toward an increase in the working rate and memory volume and a decrease in the sizes of telecommunication systems necessitate the development of electronic devices based on new principles and, hence, the corresponding technologies for implementation. Physical problems that impede the application of conventional methods in new problems are analyzed, and possible solutions are proposed.
An Oxide over Titanium metal resistance bolometer technology developed by NMRC (Ireland) has been transferred to the X-FAB UK CMOS foundry at Plymouth, UK. Prototypes of the bolometers have been manufactured in the X-FAB production facility and tests show performance comparable with the NMRC prototypes. The bolometer design has been integrated with a CMOS read-out chip and the first wafers are currently being packaged for evaluation. The development of a low cost thermal imaging camera using the detector is under way. We present an overview of the detector and camera design, together with preliminary results from the detector test programme. The work is partly funded by the European Union IST programme.
We have developed platinum (Pt) deposition and chlorine-based Reactive Ion Etch (RIE) processes that are needed to deposit, pattern and embed electrodes deep within a MEMS process flow. Various combinations of chlorine-based gases were tested to find the optimum gas mixture for RIE. A 1: 0.4 mixture ratio of pure chlorine to argon and 100-150 Watts of RF microwave power were found to be optimum conditions for the RIE of platinum metal. The addition of argon gas to chlorine was found to contribute to the anisotropic etching of platinum, obtaining vertical shaped sidewall patterns. A simple model of the platinum etching mechanism is proposed. Following the plasma enhanced formation of platinum and chlorine ions, volatile products of platinum chlorides were formed and driven away at elevated temperature. As a demonstration of our RIE process, micron-sized platinum patterns with vertical sidewalls were fabricated. Etch chemistry was investigated using ToF SIMS analysis. This etch technique will be useful to device developers intending to use the unique properties of platinum metal as an electrode that is deeply embedded within a MEMS process flow.
LETI LIR has been involved in Amorphous Silicon uncooled microbolometer development for a few years. This paper reports recent progress that have been carried out both in technological and product field. Due to the very particular features of LETI LIR technology, large fill factor, high thermal insulation, associated with small thermal time constant, can be achieved, resulting in a large detector responsivity. In addition, pulsed bias has been introduced showing performance improvement in terms of power consumption, reliability, faster thermal response. A model has been developed which accounts for these improvements. Electro-thermal results obtained from an IRCMOS 256 X 64, 47 micrometers detector sizes, laboratory prototype show that NETD less than 50 mK at f/1 can be obtained even at a high video scanning rate, that is compatible with micro scanning techniques.
This paper provides an update of 17 micron pixel pitch uncooled microbolometer development at DRS. Since the introduction of 17 micron pitch 640x480 focal plane arrays (FPAs) in 2006, significant progress has been made in sensor performance and manufacturing processes. The FPAs are now in initial production with an FPA noise equivalent temperature difference (NETD), detector thermal time constant, and pixel operability equivalent or better than that of the current 25 micron pixel pitch production FPAs. NETD improvement was achieved without compromising detector thermal response or thermal time constant by simultaneous reduction in bolometer heat capacity and thermal conductance. In addition, the DRS unique "umbrella" microbolometer cavities were optically tuned to optimize detector radiation absorption for specific spectral band applications. The 17 micron pixel pitch FPAs are currently being considered for the next generation soldier systems such as thermal weapon sights (TWS), vehicle driver vision enhancers (DVE), digitally fused enhanced night vision goggles (DENVG) and unmanned air vehicle (UAV) surveillance sensors, because of overall thermal imaging system size, weight and power advantages.
A 128 by 128 pixel bolometer infrared focal plane array using thin film titanium has been developed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. Since the thermal conductance of the bolometer detector is minimized, the temperature of the detector itself is increased by applying the bias current. Under the present operating conditions of the titanium bolometer, this temperature increase becomes about 30 degrees Celsius. The influence of this bias heating on device destruction and degradation was experimentally investigated and is discussed. The noise equivalent temperature difference obtained with the device is 0.07 degrees Celsius. Since the fabrication process is silicon-process compatible, costs can be kept low.
RVS has made a significant breakthrough in the development of a 640 × 512 array with a unit cell size of 20mum × 20 mum and performance equivalent to that of the 25mum arrays. The successful development of this array is the first step in achieving mega-pixel formats. This FPA is designed to ultimately achieve performance near the temperature fluctuation limited NETD (
We have developed a high temperature Pt etching by using a titanium (Ti) mask layer in oxygen (O2)-containing plasma. The high temperature Pt etching technique has been employed to fabricate a stacked capacitor with a critical dimension (CD) of 0.15 μm. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 μm and, thus, the storage node electrode with the CD of 0.15 μm could not be fabricated. Accordingly, we have proposed novel techniques to surmount the above difficulties.
A 128 by 128 pixel bolometer infrared focal plane array using thin film titanium has been developed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. Since the thermal conductance of the bolometer detector is minimized, the temperature of the detector itself is increased by applying the bias current. Under the present operating conditions of the titanium bolometer, this temperature increase becomes about 30 degrees Celsius. The influence of this bias heating on device destruction and degradation was experimentally investigated and is discussed. The noise equivalent temperature difference obtained with the device is 0.07 degrees Celsius. Since the fabrication process is silicon-process compatible, costs can be kept low.© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Today, a large number of uncooled infrared detector developments are under progress due to the availability of silicon technology that enables realization of low cost 2D IR arrays. LETI/LIR, which has been involved in this field for a few years, has chosen resistive amorphous silicon as thermometer for its uncooled microbolometer development. After a first phase dedicated to acquisition of the most important detector parameters in order to help the modeling and technological development, an IRCMOS laboratory model (256 X 64 with a pitch of 50 micrometer) was realized and characterized. It was shown that NETD of 90 mK at f/1, 25 Hz and 300 K background can be obtained with high thermal insulation (1.2 107 K/W).© (1998) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
As we enter the era of ultra‐large‐scale integrated circuit manufacture, plasma etching grows more important for fabricating structures with unprecedented dimensions. For feature sizes below 1 μm and aspect ratios (depth/width) much larger than one, etching rates have been observed to depend on aspect ratio and pattern density. Such dependencies tend to increase the cost of manufacturing because even small changes in device design rules, cell design, or wafer layout can result in time‐consuming, new plasma process development. In addition, microscopically nonuniform etching affects the trade‐off between chips lost from failure to clear and chips lost by damage from overetching. Although aspect ratio and pattern dependent etching have been observed for a large variety of material systems and processing conditions, the fundamental causes underlying these effects are poorly understood. Partly, this results from use of confusing and conflicting nomenclature and a lack of careful, quantitative comparisons between experiment and theory. In this article we review recent literature on microscopic uniformity in plasma etching and carefully define terminology to distinguish between aspect ratio dependent etching (ARDE) and the pattern dependent effect known as microloading. For ARDE, we use dimensional analysis to narrow the range of proposed mechanisms to four which involve ion transport, neutral transport, and surface charging. For microloading, we show that it is formally equivalent to the usual loading effect, where the reactant concentration is depeleted as a result of an excessive substrate load.
By cooling substrates to low temperatures (-40 °C), plasma etching of AlGaAs/AlAs/GaAs structures is performed in an ion‐activated, surface reaction limited regime. As a result, microscopic and macroscopic uniformity are vastly improved and etching is independent of gas flow patterns, plasma geometry, and reactor loading. Because the reactant is concentrated on the surface, etching rates remain large.
In a metal film infrared microbolometer, the responsivity is improved by high bias current to compensate for its low-temperature coefficient of resistance (TCR). However, what are the upper limits of this current without damaging the microbolometer element is not well understood. To study the effects of large bias current, we performed the destructive I-V measurements on an element of a 16 times 16 Ti-microbolometer array developed at our laboratory and report here the experimental observations of its electrical and physical damages. In this study, we performed the I-V measurements repeatedly on a microbolometer element and increased the final bias current in steps of 50 muA in each repetition. The effect of the heating due to I<sup>2</sup>R power dissipation has been analyzed at each step by monitoring I-V characteristics, specific detectivity and physical health. We report a significant decrease in the detectivity when bias stress is increased beyond 450 muA, which corresponds to the element temperature of 370degC. Further, we found that the resistance started decreasing, when the power dissipated and the element had increased to about 2.5 mW, resulting in a peaked I-V characteristics. This corresponds to the bias stresses more than 650 muA. Using a new I-V model, we extracted the temperature to be about 750degC at these peaks. A further increase in bias stress has resulted in the complete physical damage of the element.
This paper experimentally demonstrates a novel technique that drastically reduces the self-heating effect in microbolometers and which can be used to enhance the response due to infrared (IR). This is accomplished by using two bolometers with tailored thermal parameters, in particular, similar thermal mass but different thermal conductivity. Test devices with responsivity of over 6000 V/W at bias voltage of 3 V have been fabricated. Results indicate that this method is robust even under considerable mismatch of device parameters. We believe that this technique would pave way for realization of relatively simple, low cost and sensitive IR detectors for use in thermometry, imaging and other IR applications.
This paper reports the implementation and comparison of two low-cost uncooled infrared microbolometer detectors that can be implemented using standard n-well CMOS processes. One type is based on a suspended n-well resistor, which is implemented in a 0.8 μm CMOS process and has a pixel size of μm with a fill factor of 13%; and the other type is based on a suspended p+-active/n-well diode, which is implemented in a 0.35 μm CMOS process and has a pixel size of μm with a fill factor of 44%. These detectors can be obtained with simple bulk-micromachining processes after the CMOS fabrication, without the need for any complicated lithography or deposition steps. The diode type detector has a measured dc responsivity () of 4970 V/W at 20 μA bias and a thermal time constant of 35.8 ms at 80 mTorr vacuum level, and it has a measured rms noise of 0.52 μV for a 4 kHz bandwidth, resulting in a detectivity (D∗) of 9.7×108 cm Hz1/2/W. The resistive n-well detector can provide the same dc responsivity at 1.68 V detector bias voltage, with about 10 times more self-heating as compared to that of the diode type detector. This detector has a measured rms noise of 0.81 μV for a 4 kHz bandwidth, resulting in a detectivity (D∗) of 8.9×108 cm Hz1/2/W, which can be improved further with higher detector bias voltages at the expense of increased self-heating. The diode type detector is better for low-cost large format infrared detector arrays, since it has a superior response even at reduced pixel sizes and lower biasing levels.
This paper investigates reactive ion etching (RIE) of sputtered tungsten films, a suitable candidate for gate metallization in compound semiconductor based high mobility channel devices, with the aim of developing a detailed understanding of the effects of etching parameters vital to reducing etch-induced damage and improving etching performance, yield, uniformity and repeatability. An Oxford Instruments PlasmaLab System 100 RIE etch tool and SF6 based chemistry in combination with various functional gases, such as N2, O2 and CHF3 was used in this study. To evaluate plasma-induced damage caused by the RIE process, GaAs based HEMT (high electron mobility transistor) type layer structures with channels buried 18nm from the surface were grown by molecular beam epitaxy (MBE). Subsequently, Van der Pauw structures were fabricated on this material and used to assess the effects of the RIE process on sheet resistivity, carrier concentration and mobility in the device channel. Etched tungsten line widths down to 25nm were obtained by electron beam lithography with Sumitomo NEB31 resist as an etch mask. The effects of etching gases of SF6+N2, SF6+O2, and SF6+CHF3, RF power, and etching temperature on etching profile and etching-induced damage were investigated.
We combine electron beam lithography (EBL) with conventional microscale metal deposition and etch process technologies, to fabricate bolometer devices with nanoscale feature critical dimensions (CDs). We report the creation of titanium (Ti) bolometer devices with 70 nm minimum feature CDs, and total bolometer film thicknesses ranging between 40 nm and 120 nm. Our new nanobolometer devices integrate with conventional CMOS and MEMS fabrication processing, to create thermally isolated sensors with nanoscale feature sizes on a 0.5 mum CMOS base process. We present temperature coefficient of resistance (TCR) data for our new devices, and report a nanobolometer TCR performance of 0.22%/K at 70 nm CDs, a TCR value comparable to figures reported for Ti-based uncooled microbolometer devices.
A novel triple-level-metal process, utilizing tungsten for
first-level metallization, has been developed for use in submicron
arrays. The contact barrier is a composite layer of sputtered and CVD
TiN, providing for good adhesion of the blanket tungsten layer. Other
process modules include tapered contact and via etches, dyed resist for
fine-line patterning, reflowed BPSG for first ILD and via-1, and
low-stress nitride passivation, providing for void-free metallization
for all three layers. Prototype 1.0-μm gate arrays have been
fabricated using this technology
The authors describe a new type of infrared (IR) focal plane
consisting of a 2-D array of microminiature bolometers (microbolometers)
fabricated, complete with readout electronics, as a monolithic silicon
chip. These focal planes require no cooling for sensitive detection of
IR radiation. The authors report high-quality IR imaging obtained with
such focal planes
The process characterization, optimization, and production
implementation of a photoresist-masked, CVD tungsten metallization
scheme is described. Statistical experimental design and response
surface methodology were used to improve the manufacturability of the
deposition and etch process steps. Repeatable deposition and etch rates
have been achieved with anisotropic sidewall profiles. Statistical
process control charts illustrating critical dimension control, as well
as various monitored deposition and etch parameters are shown to
document the performance of the integrated process. Finally defect
densities of tungsten and aluminum interconnect are compared to
ascertain the relative cleanliness and manufacturability of each process
The characteristics of SF<sub>6</sub>/He plasmas used to etch TiW
have been studied with statistically designed experiments using a Tegal
804 single wafer system. Two processes were developed using both
positive and negative photoresist as the mask material for etching TiW.
The goal was to consolidate both processes into one. A two-phase
experimental approach was taken to generate the processes. In phase 1 a
fractional factorial screening experiment was used to identify key
factors, and in phase 2 a mixture experiment was used for process
optimization. The fractional factorial experiment was initially used to
study the effects of reactor pressure, RF power, SF<sub>6</sub>/He gas
ratio, overetch time, and hard bake. The results of this initial
experiment were used to identify the appropriate levels for the main
process parameters. Then, at these parameter levels, a mixture
experiment was conducted using the partial pressures of SF<sub>6</sub>,
He, and the nitrogen ballast as the design variables. Since the total
pressure in the system is fixed, these three variables are the
components of a mixture, and thus form a constrained design space for
the experiment. Quadratic and special cubic response surface models were
generated for the following responses: TiW etch rate, photoresist
etch-rate, selectivity between the TiW and photoresist, uniformity of
all etch rates and selectivities, and critical dimension control for the
photoresist and TiW. Contour plots for all responses as a function of
the partial pressure of SF<sub>6</sub>, He, and nitrogen ballast were
generated. The contours from these empirical models were analyzed
jointly to optimize the processes
A 128×128 element bolometer infrared image sensor using thin
film titanium is proposed. The device is a monolithically integrated
structure with a titanium bolometer detector located over a CMOS circuit
that reads out the bolometer's signals. By employing a metallic material
like titanium and refining the CMOS readout circuit, it is possible to
minimize 1/f noise. It is demonstrated that the use of low 1/f noise
material will help increase bias current and improve the S/N ratio.
Since the fabrication process is silicon-process compatible, costs can
be kept low
Uncooled IR Nanobolometers Fabricated by Electron Beam Lithography and a MEMS
- S F Gilmartin
S.F. Gilmartin, et al., Uncooled IR Nanobolometers Fabricated by Electron Beam Lithography and a MEMS/CMOS Process, in: Proc. NANO '08. 8th IEEE Conference on Nanotechnology, 2008, pp. 131–134.
& Technology B: Microelectronics Processing and Phenomena
- R A Gottscho
- C W Jurgensen
- D J Vitkavage