A High-Linearity Sigma-Delta Topology Suitable for Low-Voltage Applications

Abstract

A Sigma-Delta topology with reduced sensitiv-ity to OTA gain nonlinearities has been introduced. The most important feature of this topology is that the signal transfer function is unity, which is relatively independent to the building block characteristics. With careful signal scal-ing, signal swings inside the loop can be suppressed to less than 50% of the reference voltage, which is highly appreci-ated by low-voltage designs. Behavior simulation revealed that requirements for OTA are quite relaxed in this topol-ogy. With an oversampling ratio of 128, the proposed third-order Σ-∆ modulator topology can achieve more than 16 bit resolution. Simulated with a 90nm CMOS technology file, more than 96dB SNR can be achieved with less than 0.5mW power dissipation in 20kHz signal bandwidth under 1 volt power supply voltage.

Full text

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A High-Linearity Sigma-Delta Topology Suitable
for Low-Voltage Applications
Libin Yao, Michiel Steyaert and Willy Sansen
ESAT-MICAS, Katholieke Universiteit Leuven
Kasteelpark Arenberg 10
B-3001 Leuven, Belgium
Phone: +32 - 16 - 32 96 20
Fax: +32 - 16 - 32 19 75
Email: libin.yao@esat.kuleuven.ac.be
Keywords— linearity, low-voltage, Sigma-Delta modula-
tor.
Abstract—A Sigma-Delta topology with reduced sensitiv-
ity to OTA gain nonlinearities has been introduced. The
most important feature of this topology is that the signal
transfer function is unity, which is relatively independent to
the building block characteristics. With careful signal scal-
ing, signal swings inside the loop can be suppressed to less
than 50% of the reference voltage, which is highly appreci-
ated by low-voltage designs. Behavior simulation revealed
that requirements for OTA are quite relaxed in this topol-
ogy. With an oversampling ratio of 128, the proposed third-
order Σ-∆ modulator topologycan achieve more than 16 bit
resolution. Simulated with a 90nm CMOS technology file,
more than 96dB SNR can be achieved with less than 0.5mW
power dissipation in 20kHz signal bandwidth under 1 volt
power supply voltage.
I. INTRODUCTION
D
technology is pacing into 100 nano meter range. As
a consequence, the power supply voltage drops be-
low 1 volt earlier than expected. On the other hand,
the portable electronics with low-voltage operation
find their big market.All these factors make the
low-voltage circuits a hot topic recently. The low
supply voltage constraint makes the analog design
more challenging due to the reduced signal swing.
As a major building block, the analog to digital con-
verter(ADC) is widely used in mixed-signal circuits.
As an interface between analog world to the digital
circuitry, ADCs are implemented with the same tech-
nology as the digital circuitry hence the power supply
voltage reduction is inevitable. The decrease of the
RIVING bythespeeddemandofdigitalcircuits,
in recent years the deep sub-micron CMOS
supply voltage obviously results analog circuits per-
formance degradation. Generally speaking, to main-
tain the same dynamic range on a system, the noise
floor should be lowered while the signal swing is re-
duced. So does the distortion components. Unfortu-
nately, as the supplyvoltage drops, thedistortiontend
to be more severe.
Among different ADCs, Sigma-Delta(Σ-∆) ADCs
are most suitable for high-resolution applications due
to their high linearity feature.
is gained by using the intrinsic linear 1-bit quan-
tizer and oversampling technique. However, the non-
idealities in the building blocks strongly affect the
performances. To design a Σ-∆ ADC, main efforts
are to fight with the non-idealities of building blocks.
The reduced supply voltage makes these constraints
even tighter. Among them, the most important one is
the distortion problem in high resolution Σ-∆ ADCs
[1]. Another problem with low-voltage design is that
lower noise-floor is required for same dynamic range
and difficulties to design building blocks [2].
The high linearity
II. IMPACTS OF DEEP SUB-MICRON CMOS
TECHNOLOGIES TO ANALOG DESIGN
With the evolvement of the CMOS technology,
analog circuits is moving into deep sub-micron
CMOS technology. The impacts deep sub-micron
technology brings to analog designers are two-fold.
Oneis thereduction ofthesupplyvoltageand another
is the more severe transistor characteristics degrada-
tion comparing to traditional long channel transistors
[3]. The low-voltage environment forces the circuit
working on relatively large signal condition. Hence
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more derivation from the biasing point and more dis-
tortion generated. On the same time, the intrinsic
gain of the MOS transistor is reduced as well, which
brings more difficulties to design high-gain ampli-
fiers.
To conclude, in deep sub-micron CMOS technolo-
gies, it is more difficult to implement high-quality
analogbuildingblocks,ormorepowershouldbeused
to achieve the same specifications, comparing to tra-
ditional long-channel CMOS technologies.
III. LINEARITY ANALYSIS OF Σ-∆ ADCS
Vo
Vi
Va Va
VoCs
Ci
Cs
Ci
gogo
Fig. 1. Switched capacitor integrator model using OTA
To gain an insight view of the non-ideality im-
pacts on the switched-capacitor Σ-∆ ADC perfor-
mance, behavior simulation is used for its clearness
and speed. The switched-capacitor integrator, the ba-
sic building block in switched-capacitor Σ-∆ ADCs,
is the vital building block that determines the overall
Σ-∆ ADC performances. For a single-ended SC in-
tegrator, shown in Fig.1, the charge balance equation
can be written as
CI·(v+
o−v+
a) = CI·(v−
o−v−
a)+CS·(vi−v−
a) (1)
Where CSand CIare sampling and integration ca-
pacitance respectively. Through out this paper, v+
and v−are used to replace v((n+1/2)T) and v((n−
1/2)T) in order to simplify the equations. The ampli-
fier is modeled by operational transconductance am-
plifier(OTA). The input and output relationship of the
OTA is
v±
Where A is the voltage gain of the OTA. For an ideal
integrator, the gain of the OTA is infinite. The equa-
tion 1 and 2 serve as the fundamental equations of
switched-capacitor integrator. Based on these equa-
tions, by adding non-idealities into them, various of
behavior simulations can be carried out.
o= −A · v±
a
(2)
A. Non-linearities modeling in Σ-∆ ADCs
There are building block non-idealities that de-
grade the performance of Σ-∆ ADCs. In the
switched-capacitor Σ-∆ ADCs,
linearities related the distortion are the non-linear
OTA gain, the non-linear capacitance and the non-
linear switch. These non-linearities generate harmon-
ics and degrade the linearity performance of the en-
tire Σ-∆ ADC. To investigate the effects of these
non-linearities, each non-linearity is modeled in the
charge balance equation in III. Then behavior sim-
ulation is performed and final results are obtained
through the simulation. Through out the paper, a sin-
glebitthird-orderΣ-∆ modulatorischosenasthetest
vehicle to carry out all simulations and comparisons.
the main non-
10
2
10
3
10
4
10
5
10
6
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
Frequency [Hz]
Power spectral density [dB/bin]
SNDR=67.3dB
Fig. 2. SimulatedSNDR ofa classic third-orderΣ-∆modulator
with b1= −0.1 b2= −0.1
In modern CMOS technologies, the MIM capaci-
tance linearity is quitegood and the non-linearswitch
problems can be solved easily. However, the non-
linearity of the OTA is getting worse with the transis-
tor feature size shrinking, making it the main source
of the non-linearity of the Σ-∆ ADCs.
B. Non-linear OTA gain modeling in Σ-∆ ADCs
The non-linearity of the OTA gain can be modeled
as
A = A0(1 + b1· vo+ b2· v2
Where AOis the DC gain of the OTA in small signal
condition. VOis the output voltage of the OTA and
b1, b2are first and second order distortion factors, re-
spectively. By using this model, the variation of the
OTA gain with the output voltage can be derived.
By replacing the gain in equation 2 with equation
3, the input-output relation of a switched-capacitor
integrator can be readily get. By applying this rela-
tion in the behavior simulation of Σ-∆ modulators,
o)
(3)
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H(z)H(z)H(z)
+
+
+
+
-
x
y
a1a2a3c3
c2
c1
Fig. 3. Proposed High-linearity single-loop third-order Σ-∆ modulator topology
the non-linearity of the Σ-∆ modulator can be simu-
lated.
Fig. 2 shows the output spectrum of a third-order
single-loop Σ-∆ modulator with a non-linear OTA
modeled with coefficient b1 = − 0.1 b2 = − 0.1.
It is clear that, from Fig.2, the gain non-linearity of
the OTA causes large harmonic distortion in the Σ-∆
modulator.
IV. HIGH-LINEARITY Σ-∆ MODULATOR
TOPOLOGY
From above analysis and simulations, the conclu-
sion could be drawn that the most non-linearity is
sourced from the non-linear OTA gain.
submicron technology, this problem is getting more
severe due to the relatively large signal swing, as
mentioned in II. It is difficult to completely solve this
problem in the circuit level. However, this problem
could bepotentiallysolvedintheΣ-∆ topologylevel,
e.g. with the proposed high-linearity Σ-∆ modulator
topology.
The high-linearity Σ-∆ modulator topology [4], as
an example, a third-order one, is shown in Fig.3. It
has some unique characteristics comparing to tradi-
tional topology [4]. The most interesting characteris-
tic is that the signal transfer function is unity, there-
fore the non-idealities in the building blocks will not
affect thesignalquality. Fig. 4showstheoutputspec-
trum of a third-order single-loop high-linearity Σ-∆
modulator with a non-linear OTA modeled with coef-
ficient b1= − 0.1 b2= − 0.1. Comparing to Fig.2,
the same coefficients are used, but in high-linearity
Σ-∆ modulator, the harmonic distortion is not vis-
ible. Another feature associated with this topology
is that the internal swing of the loop can be signif-
In deep-
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10
3
10
4
10
5
10
6
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
Frequency [Hz]
Power spectral density [dB/bin]
SNDR=98.2dB
Fig. 4.
modulator with b1= −0.1 b2= −0.1
Simulated SNDR of a high-linearity third-order Σ-∆
icantly reduced comparing to classic one. Shown in
Fig.5, outputsofthreeintegratorsofthehigh-linearity
Σ-∆ modulator are all smaller than half of the refer-
ence voltage. This simply ease the OTA design in
low-voltage environment. As in low-voltage environ-
ment, the output swing is limited by the supply volt-
age and the saturation voltage of the transistor. Or for
the same output swing of the OTA, higher reference
voltage can be chosen, which eventually reduce the
power consumption.
Fig.8 and Fig.7 show the gain requirement for the
OTA used in the classic Σ-∆ modulator and high-
linearity Σ-∆ modulator, respectively. It can be seen
for noise-shaping only, the OTA gain of 30dB to
40dB is enough for 95dB SNR. While in classic Σ-
∆ modulator topology, much higher gain is requested
to suppress the distortion caused by the non-linear
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OTA gain.
quired. However, in the high-linearity Σ-∆ modula-
tor topology, the OTA gain requirement is only de-
fined by noise-shaping performance, which is only
30dB. With such relaxed requirements for the OTA,
drastically scaling-down can be done to reduce the
power consumption, making the proposed topology
an ideal topology for low-voltage low-power Σ-∆
ADC.
Typically more than 60dB gain is re-
0123456
x 10
4
−1
0
1
0123456
x 10
4
−1
0
1
Output swing [Normalized to Vref]
0123456
x 10
4
−1
0
1
Samples
Fig. 5. Simulated integrator output swings of a high-linearity
third-order Σ-∆ modulator with a SNR=100dB and OSR=128
0123456
x 10
4
−1
0
1
0123456
x 10
4
−1
0
1
Output swing [Normalized to Vref]
0123456
x 10
4
−1
0
1
Samples
Fig. 6.
order Σ-∆ modulator with a SNR=100dB and OSR=128
Simulated integrator output swings of a classic third-
V. CIRCUIT IMPLEMENTATION
The proposed Σ-∆ modulator can be implemented
using switch-capacitor circuits. The only difference
1020304050 607080
80
85
90
95
100
105
110
OTA gain [dB]
SNR [dB]
Fig. 7.
SNR vs. OTA gain
High-linearity single-loop third-order Σ-∆ modulator
102030 4050607080
80
85
90
95
100
105
110
OTA gain [dB]
SNR [dB]
Fig. 8. Classical single-loop third-order Σ-∆ modulator SNR
vs. OTA gain
with the classic topology is that an additional sum-
mer is needed to sum the feedforwarded signal to-
gethertothequantizer. ShowninFig.9,thesummeris
implemented with a passive switched-capacitor net-
work. The rest circuits are the same with the clas-
sic topology. The OTA used is a current-mirror OTA
with gain enhancement [5], which provides rail-to-
rail output swing with moderate gain and very com-
petitive power consumption. Simulated with a 90nm
CMOS technology file, the proposed Σ-∆ modula-
tor achieves 16bit resolution in 20kHz bandwidth
and consumes less than 0.5mW in 1V supply. The
full-circuit simulated output spectrum is presented in
Fig.10.
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+
-+
-+
-+
-+
-+
-+
-+
-
C1d
C1d
C1d
C1
C2C1d
C1
C2
C2d
C1d
C1
C2
C2d
C1d
C1
C2
C2d
C1d
C1
C2
C2d
C1d
C2
C1
C2d
C1d
C2
C1
C2d
Ci1
C1
C2
Ci1
Cis
Cs1
Ci2
Ci2
Cs2
Cs2
Ci3
Ci3
Cs3
Cs3
Cf3
Cf2
Cf1
CF0
Cf3
Cf2
Cf1
Cf0
CMoCMi
CMi
CMi
CMiCMo
CMo
CMi
CMi
VrefpVrefn
Vrefn Vrefp
inp
inn
OTA1OTA2 OTA3
C2d
C2d
Fig. 9. Circuits implementation of the high-linearity Σ-∆ modulator
10
3
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4
10
5
10
6
−160
−140
−120
−100
−80
−60
−40
−20
0
Frequency [Hz]
Power spectral density [dB/bin]
Fig. 10.
circuits
Full circuit simulated output spectrum of proposed
VI. CONCLUSION
A high-linearity Σ-∆ modulator topology is pre-
sented in this paper. Main features of this topology
are the unity signal transfer function and low internal
swings.
These features make this topology an ideal topol-
ogy for low-voltagelow-power Σ-∆ modulator. With
an oversampling ratio of 128, the proposed third-
order Sigma-Delta modulator topology can achieve
more than 16bit resolution. Simulated with a 90nm
CMOS technology file, more than 96dB SNR can be
achieved with less than 0.5mW power dissipation in
20kHz signal bandwidth under 1 volt power supply
voltage.
REFERENCES
[1] K-L. Lee, R. G. Meyer, “Low-Distortion Switched-Capacitor Filter
Design Techniques,” IEEE J. Solid-State Circuits, vol. sc-20, pp.
1103 - 1113, Dec. 1985.
[2] W. Sansen, M. Steyaert, V. Peluso, and E. Peeters, “Toward sub 1V
analog integrated circuits in submicron standard CMOS technolo-
gies,” in proc. IEEE Int. Solid-State Circuits Conf., vol. XLI, pp.
186 - 187, Feb. 1998.
[3] W. Sansen, “Challenges in Analog IC Design in Submicron CMOS
Technologies,” Analog and Mixed IC Design,IEEE-CAS Region 8
Workshop, pp.72-78, Sep. 1996.
[4] J. Silva, U. Moon, J. Steensgaard and G. C. Temes, “A Wideband
low-distortion Delta-Sigma ADC topology,” Electronics Letters,
vol.37, no. 12, pp. 737-738, Jun. 2001.
[5] L. Yao, M. Steyaert and W. Sansen, “A 0.8-V, 8-µW CMOS OTA
with 50-dB gain and 1.2-MHz GBW in 18-pF load,” Proceedings
of the 29th European Solid-State Circuits Conference, Sep. 2003.
311