A New SoC Test Scheduling Algorithm using Random Insertion

ABSTRACT This paper presents a new SoC (System-on-Chip) test scheduling algorithm. Reducing the test application time is an important issue for a core-based SoC test. In this paper, each core is represented by a rectangle whose height is equal to the TAM width and width is equal to the test time. 'One-element-exchange' algorithm is used for optimizing the test time of each core, and 'RAIN' algorithm is used for optimizing the test time of a SoC. The RAIN algorithm uses a sequence pair data structure to represent the placement of rectangles, and obtains the optimized results by inserting into the random position of sequence pair sequence. The results of the experiments conducted on ITC '02 SoC benchmarks show that the proposed algorithm gives the shortest test application time than earlier researches for most of the cases.

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    ABSTRACT: We present optimal solutions to the test scheduling problem for core-based systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application time is minimized. We show that the test scheduling decision problem is equivalent to the m-processor open shop scheduling problem and is therefore NP-complete. However a commonly encountered instance of this problem (m=2) can be solved in polynomial time. For the general case (m>2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver available in the public domain. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally, we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11/2000; 19(10-19):1163 - 1174. DOI:10.1109/43.875306 · 1.20 Impact Factor
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    ABSTRACT: The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 01/1997; DOI:10.1109/43.552084 · 1.20 Impact Factor
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    ABSTRACT: In this paper, the modeling of system-on-a-chip (SOC) test optimization has been formulated with different precedence, resource and core constraints. A neural network combined with heuristic algorithm has been developed to solve the large size SOC test problems. As demonstrated by the results that computer implement the developed method can not only solve the large size SOC test problems, but is also capable of finding the optimal solutions within reasonable computing time.
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