Article

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

Journal of Semiconductors 05/2011; 32. DOI: 10.1088/1674-4926/32/4/045010

ABSTRACT A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions, respectively. The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable. In order to further improve the accuracy of phase alignment and phase shift, a VCO design based on a novel quick start-up technique is proposed. A new delay partition method is also adopted to improve the speed of the post-scale counter, which is used to realize the programmable phase shift and duty cycle. A prototype chip implemented in a 0.13-m CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz. The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps, respectively. The settling time is approximately 2 s.

0 Bookmarks
 · 
177 Views
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper describes a low jitter phase-locked-loop (PLL) with a 4<sup>th</sup> order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator (VCO) gain over process variations, in addition to compensation for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noise immunity with a wide (5:1) VCO frequency range, without the need for band switching or calibration routines. This PLL is fabricated in a 0.18 μm CMOS logic process and exhibits <4 ps rms accumulated jitter.
    Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004; 11/2004
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A fully integrated 1.175-2-GHz differentially tuned frequency synthesizer aimed for digital video broadcasting-terrestrial tuners is implemented in a 0.18-mum CMOS process. To maintain phase-noise optimization and loop stability over the entire output frequency range, techniques of constant loop bandwidth are proposed. The voltage-controlled oscillator gain K <sub>VCO</sub> and band step f <sub>res</sub> are both maintained by simultaneously adjusting the sizes of switched capacitors and varactors. Charge pump current I <sub>CP</sub> is programmed to compensate the variation of the division ratio N . The measured results show an in-band phase noise of -97.6 dBc/Hz at a 10-kHz offset and an integrated phase error of 0.63 <sup>deg</sup> from 100 Hz to 10 MHz. The measured variations of K <sub>VCO</sub> and f <sub>res</sub> are less than 12.5% and 4.5%, respectively. The variations of the measured phase noise at 10-kHz and 1-MHz frequency offsets are less than 1 dB. The measured 3-dB closed-loop bandwidth is 110 kHz and the variation is less than 9%. The chip draws 10-mA current from a 1.8-V supply while occupying a 2.2-mm<sup>2</sup> die area.
    IEEE Transactions on Microwave Theory and Techniques 05/2009; · 2.23 Impact Factor
  • [Show abstract] [Hide abstract]
    ABSTRACT: A 500MHz supply noise insensitive CMOS PLL with a voltage regulator using a capacitive DC-DC converter (VRCC) achieves a jitter level of 30ps rms for quiet supply, and 42ps rms for 600mV supply noise, with a locking range of 110MHz to 850MHz. The worst case PSNR using VRCC shows -45dB in the medium frequency. The circuit is fabricated in a 0.35µm, 3.3V standard digital CMOS process and occupies 2.2mm<sup>2</sup>. The power consumption at 3.3V including buffer is 42mW at 500MHz.
    Solid-State Circuits Conference, 2000. ESSCIRC '00. Proceedings of the 26th European; 10/2000

Full-text (2 Sources)

View
123 Downloads
Available from
Jun 5, 2014