Transient processes in a Ge/Si hetero-nanocrystal p-channel memory

Abstract

Transient processes of Ge/Si hetero-nanocrystal floating gate memories are simulated numerically. Compared with Si nanocrystal memories, Ge/Si hetero-nanocrystal memories show similar writing and erasing efficiency with a weaker writing saturation and markedly improved retention characteristics.

Full text

Page 1

Transient processes in a Ge/Si hetero-nanocrystal p-channel memory
Dengtao Zhao, Yan Zhu, Ruigang Li, Jianlin Liu*
Quantum Structures Laboratory, Department of Electrical Engineering, University of California, Bourns Hall A219, Riverside, CA 92521, United States
Received 6 June 2005; received in revised form 21 January 2006; accepted 21 January 2006
Available online 13 March 2006
The review of this paper was arranged by Prof. C. Tu
Abstract
Transient processes of Ge/Si hetero-nanocrystal floating gate memories are simulated numerically. Compared with Si nanocrystal
memories, Ge/Si hetero-nanocrystal memories show similar writing and erasing efficiency with a weaker writing saturation and markedly
improved retention characteristics.
? 2006 Elsevier Ltd. All rights reserved.
PACS: 72.20.Jv; 73.21.La; 73.90.+f; 74.50.+r
Keywords: Hetero-nanocrystal; Memory; Transient
1. Introduction
Si nanocrystals (NCs) as discrete storage nodes are very
promising to replace conventional continuous metal or
poly-Si floating gate in a metal-oxide-semiconductor-field-
effect-transistor (MOSFET), offering the advantages of
smaller device size, higher programming speed and lower
operation voltage [1–5]. As scaling continues to reduce
the tunneling oxide thickness for lower operation voltages,
the simultaneous realization of a long retention time as well
as a high writing/erasing speed is very important, but, chal-
lenging. Due to the quantum confinement effect, either the
valence band edge (Ev) or the conduction band edge (Ec) of
the Si NC is higher than that of the Si substrate, which
degrades the retention characteristics as the charge stored
in the NC can easily leak back to the substrate. Therefore
it is believed that the long charge storage occurs mainly in
the defect-related traps instead of in the conduction or
valence bands [3,4,6]. However, the defect-related traps
are sensitive to operation temperature and also difficult
to be controlled in device fabrication. Therefore, good con-
sistency in device performance is not easily achieved, espe-
cially for devices containing only several or even one
nanocrystal storage node. Recently, Ge/Si hetero-nano-
crystals (HNC) were proposed to replace Si NCs as the
floating gate [7] for a p-channel memory, using the quan-
tum well formed by control oxide/Ge/Si to confine a hole
in a Ge dot region. Since Evof Ge is lower than that of a
Si dot, the hole in retention mode should first be thermally
excited to a certain energy level higher than the valence
band edge of the substrate before tunneling occurs. There-
fore, retention can be markedly improved without sacrific-
ing writing/erasing efficiency.
Although writing/erasing and retention time [7] and
threshold voltage shift [8] of a Ge/Si HNC memory have
been systematically investigated, research on the dynamic
characteristics is still lacking. A Ge/Si HNC memory can
behave differently in real operation because both Coulomb
blockade effect and quantum confinement effect are differ-
ent from those in a Si NC memory device. The aim of this
work is to reveal the time-dependent dynamic processes in
writing/erasing and retention of a Ge/Si hetero-nanocrystal
0038-1101/$ - see front matter ? 2006 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2006.01.008
*Corresponding author. Tel.: +1 951 8277131; fax: +1 951 8272425.
E-mail address: jianlin@ee.ucr.edu (J. Liu).
www.elsevier.com/locate/sse
Solid-State Electronics 50 (2006) 362–366

Page 2

(HNC) memory, demonstrating the advantage of a Ge/Si
HNC memory over a Si NC memory.
2. Theory and model
In principle, all of the transient processes in this paper
are based on a relation as given by:
Qðt þ DtÞ ¼ QðtÞ ? It? Dt;
where Q, t, Dt and Itare the charge in the nanocrystal, the
time, the time step and the transient tunneling current,
respectively. The charge in the nanocrystal deforms the
electrical potential profile in the device and, thus, influences
the band structure and in turn the tunneling current. Dur-
ing each step, the electrical potential is derived by solving
Poisson equation using finite difference method with the
presence of the charge in the nanocrystal. Based on this po-
tential profile, the tunneling probability is calculated by the
transfer matrix method [9,10].
The tunneling current density is given by [11,12]:
Z
where f(E) is the impact frequency, q(E) the two-dimen-
sional (2D) density of states, F(E) the Fermi–Dirac distri-
bution function and T(E) the tunneling probability
obtained from the transfer matrix method, respectively.
Eshiftis the Si valence (for writing process) or conduction
band (for erasing process) shift due to the quantum con-
finement effect from the small size of the nanocrystal.
The impact frequency reads [11]:
?
where ? h, mSi,?, eox, Fox, and eSiare the reduced Planck’s
constant, the hole (or electron) effective mass perpendicular
to the substrate, the dielectric constant of SiO2, the surface
electric field in the SiO2layer, and the Si dielectric constant,
respectively. The density of states for a 2D confined hole or
electron gas is [11]:
qðEÞ ¼mSi;==
ð1Þ
J ¼ q
Eshift6E
TðEÞfðEÞqðEÞFðEÞdE;
ð2Þ
fðEÞ ¼ 0:6 ?
2q
ð3p? hmSi;?Þ1=3
eoxFox
eSi
?2=3
;
ð3Þ
p? h2;
ð4Þ
where mSi,//is the hole or electron effective mass in the con-
fined plane of the accumulation or the inversion layer of
the substrate. The surface field in the oxide layer Foxis de-
rived by iteratively solving Poisson equation with a finite
difference technique. Only the electrons or holes in the
accumulation or inversion layer with energy higher than
the conduction or valence band edge can tunnel to the
nanocrystals.
The retention time (s) of the charge storage is derived
from the following expression:
s ¼
1
P1
i¼nexp
?ðEi?E0Þ
kBT
??
fðEiÞTðEiÞ
;
ð5Þ
where Eiand E0are the ith excited state and ground state
(for holes) in the hetero-nanocrystal respectively, and kBis
Boltzmann’s constant. The integer number, ‘n’, is the quan-
tum number from which the wave function of the hole
spreads over both Ge and Si regions of the hetero-nano-
crystal. Note Enis automatically greater than Evof Si.
Thus, the states with quantum number greater than ‘n’
can tunnel to the Si substrate. The term expð?ðEi?E0Þ
Eq. (5) represents the de-trapping coefficient, since a hole
confined in a Ge dot region should be first thermally acti-
vated to the nth excited state before it can tunnel to the
substrate. This process is very similar to the de-trapping
process described in the paper of She and King [6]. The ei-
gen energy levels and corresponding wave functions are
calculated using an improved shooting method [13] with
the effective mass approximation model. Based on the eigen
energies the Weinberg’s impact frequency f(Ei) can be writ-
ten as [12]:
fðEiÞ ¼Ei? E0
h
where h is Planck’s constant. For all the calculations, the
control oxide is fixed at 5 nm so that tunneling through
control oxide can be disregarded since tunneling probabil-
ity strongly depends on the barrier thickness.
The source-to-drain current (IDS) calculation is based on
a linear model using a small drain-to-source voltage, VDS:
kBT
Þ in
;
ð6Þ
IDS¼ ?lSurfQSurfVDSW
where lSurf, QSurf, W and L are the carrier mobility in the
inversion layer, charge in the inversion layer, the channel
width and the channel length, respectively. QSurfis ob-
tained using
L;
ð7Þ
QSurf¼ eoxFoxWL.
In our simulations, the channel length and width are as-
sumed to be both 1 lm, and the mobility lSurfis taken as
400 cm2/Vs. VDSis chosen as 0.01 V which is sufficiently
small so that the potential from the control gate voltage
is not deformed by it.
The threshold voltage shift of the device is defined as the
gate voltage when the hole density near the interface of the
tunneling oxide/substrate reaches the value of the density
deep in the substrate. The shift is then derived by compar-
ing the two threshold voltages for a charged and uncharged
memory, respectively.
ð8Þ
3. Results and discussion
The writing transient processes at ?4 and ?6 V are
shown in Fig. 1 for (a) the current density, (b) sheet charge
density in the floating gates (Ge/Si = 5 nm/3 nm and
Si = 8 nm) and (c) the transient threshold voltage shift
(DVth) of the devices. The dot density is kept as a constant
of 6 · 1011cm?2. The tunneling oxide thickness (Tox) is
2.0 nm. As writing continues, the injection efficiency
D. Zhao et al. / Solid-State Electronics 50 (2006) 362–366
363

Page 3

decreases due to the repulsion between the stored charge
and the incoming charge, exhibiting a saturation feature
in the writing curves for both Ge/Si HNC and Si NC mem-
ory devices. Fig. 1(a) indicates no evident difference
between the writing currents for the Ge/Si HNC device
and the Si NC device. However, as shown in Fig. 1(b), writ-
ing saturation for the Ge/Si HNC device is weaker than
that of the Si dot device. This is attributed to the difference
of the charging energy between a Si dot and a Ge/Si HNC
of the same size. Since the charging energy for a NC is pro-
portional to the reciprocal of its self-capacitance, and a Ge/
Si hetero-dot possesses a larger self-capacitance than a Si
dot of the same size due to the higher dielectric constant
of Ge than Si, the charging energy for a Ge/Si HNC is
higher than for a Si NC. The self-regulated writing process
limits the charge amount that can be injected to the NC
floating gate. In other words, the maximum threshold volt-
age shift (DVth) due to the stored charge amount is self-lim-
ited at a given writing voltage. The ultimate value of DVth
as a function of writing voltage is shown in Fig. 1(c). One
observes that with lower writing voltage, the Si dot device
shows a lower DVthvalue than its Ge/Si hetero-dot coun-
terpart. However, the Ge/Si HNC memory exhibits a DVth
value closer to that for a Si NC memory as the gate voltage
increases. This is because writing saturation is stronger for
Si dot memory than Ge/Si hetero-dot memory, which lim-
its the charge (hole) amount in the NCs at lower writing
voltage. Since DVthis proportional to the charge stored
in the floating gate, larger charge quantity leads to larger
DVth, as shown in Fig. 1(c).
The effect of the size of the Ge component on the writing
process is shown in Fig. 2, where the transient threshold
voltage shift is given as a function of time. It is found that
a faster DVthincrease can be achieved by using smaller Ge
dots on top of Si dots. Our calculation has shown that DVth
for a Ge/Si HNC memory device depends quite signifi-
cantly on the sizes of the Ge dot and the Si dot [8]. Smaller
Ge dots introduce larger DVth [8], i.e., larger screening
effect from the trapped charge on the gate voltage, which
consequently depresses the writing process more remark-
ably than the cases of larger Ge dots.
The comparison of the erasing processes between a Ge/
Si HNC memory and a Si NC memory is shown in Fig. 3(a)
and (b). The tunneling oxide is fixed at 2.0 nm for both
memories. For simplicity, it is assumed that each dot is
occupied by one hole only. The nominal size of the dot is
kept at 8 nm. Although the initial erasing currents are dif-
ferent for a Ge/Si HNC memory and a Si NC memory as
shown in Fig. 3(a), it is clear that the erasures for Si NC
0.
Ge
Ge
Ge
0.
10-5
10-4
Writing Time (s)
10-3
10-2
10-1
0.0
0.1
0.2
0.3
4
5
0.6
ΔVth (V)
Ge/Si: Si=3 nm
=3 nm
=4 nm
=6 nm
TOX=2 nm
Fig. 2. Threshold voltage shift evolution during writing for a Ge/Si
hetero-nanocrystal memory. The writing voltage is –6 V and the tunneling
oxide is fixed at 2 nm.
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
0
20
40
60
80
100
120
Writing Current (μA/cm
2)
Writing Time (s)
Ge/Si, -4 V
Ge/Si, -6 V
Si, -4 V
Si, -6 V
Ge/Si HNC: 5 nm/3 nm
Si NC: 8 nm
Tox=2 nm
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
0.0
2.0
4.0
6.0
8.0
Charge Density (10
11 q0/cm
2)
Writing Time (s)
Ge/Si, -4 V
Ge/Si, -6 V
Si,
Si,
-4 V
-6 V
Ge/Si HNC: 5 nm/3 nm
Si NC: 8 nm
Tox=2 nm
-6 -5-4 -3 -2 -101
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
ΔVth (V)
Gate Voltage (V)
Ge/Si=5 nm/3 nm
Si=8 nm
Dot Density=6 x 1011cm-2
TOX=2 nm
(c)
(b)
(a)
Fig. 1. Writing transient for Ge/Si hetero-nanocrystal memory and Si
nanocrystal memory. (a) The writing current as a function of time, (b) the
charge density in floating gate as a function of writing time, and (c) the
threshold voltage shift as a function of gate voltage.
364
D. Zhao et al. / Solid-State Electronics 50 (2006) 362–366

Page 4

and Ge/Si HNC devices are almost the same at the same
erasing voltage in Fig. 3(b). This is due to the fact that
the charge quantity in the floating gate is the time integral
of current. Therefore, the initial higher current does not
contribute significantly to the charge density in the floating
gate. It can also be found in Fig. 3(b) that when the erasing
voltage decreases from 6 to 4 V, the erasing speed decreases
accordingly by a factor of about six. The transient DVth
during erasure at 6 V for a Ge/Si HNC memory with differ-
ent Ge dot size is shown in Fig. 4, where no simple trend
for erasing a Ge/Si HNC memory can be found. This is
due to the combination of quantum mechanical effect and
charge density-dependent potential distortion. Since smal-
ler dot leads to stronger quantum confinement and Cou-
lomb blockade effect, which raise the ground state energy
and hinder electron current from substrate to nanocrystals.
In the meantime, smaller dot possesses higher charge den-
sity, which distorts the potential strongly and favors faster
erasing. The competition of these two factors leads to an
optimized erasing condition.
Fig. 5 shows the simulated gate voltage sweeping mea-
surement. The source–drain current (IDS) is recorded dur-
ing the gate voltage sweep with a sweep speed 0.2 V/s.
Two memory devices with different tunneling oxide thick-
nesses (2 and 3 nm, respectively) are investigated. Clear
hysteresis loops can be found, indicating the memory effect.
It is interesting to note that the saturated source–drain cur-
rent in the case of a thinner (2 nm) tunneling oxide is much
lower than the case in which a thicker (3 nm) tunneling
oxide is used. This originates from the rapid charging
through a thinner tunneling oxide. The charge in the float-
ing gate accumulates very fast and consequently strongly
screens the gate potential so that the potential in the chan-
nel does not increase any longer. Therefore, the charge den-
sity and the channel current do not respond to the gate
voltage increase.
The retention characteristics for a Ge/Si HNC and a Si
NC memory device are shown in Fig. 6, where the tunnel-
ing oxide is fixed at 2.0 nm for all the devices involved. The
initial hole number is assumed to be one in each nanocrys-
tal. One observes that the retention time for a smaller Ge/
Si HNC is shorter than that for a larger HNC, which is
attributed to the quantum confinement effect that contrib-
utes more for the device with smaller dots. It is notable that
10
-9
10
-8
10
-7
10
-6
10
-5
0
160
320
480
640
800
960
Erasing Current (mA/cm2)
Erasing Time (s)
Ge/Si, 4 V
Ge/Si, 6 V
Si, 4 V
Si, 6 V
Ge/Si=5 nm/3 nm
Si=8 nm
Tox=2 nm
10-9
10-8
10-7
10-6
10-5
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Charge Density (1011 q0/cm2)
Erasing Time (s)
Ge/Si 4 V
Ge/Si 6 V
Si 4 V
Si 6 V
Ge/Si=5 nm/3 nm
Si=8 nm
Tox=2 nm
(a)
(b)
Fig. 3. Comparison of the erasing transients between Ge/Si hetero-
nanocrystal and Si nanocrystal memory devices. (a) The transient erasing
current at 4 and 6 V, respectively and (b) charge density in floating gate as
a function of erasing time.
10-9
10-8
10-7
10-6
0.0
0.2
0.4
0.6
ΔVth (V)
Erasing Time (s)
Ge/Si: Si= 3 nm
Ge= 6 nm
Ge=4 nm
Ge=3 nm
TOX= 2nm
Fig. 4. Threshold voltage shift evolution during erasing Ge/Si hetero-
nanocrystal memories with different Ge dot sizes. The erasing voltage is
6 V and the tunneling oxide is fixed at 2 nm.
-12 -10-8-6 -4-202468 10
10
-15
10
-13
10
-11
10
-9
10
-7
10
-5
10
-3
10
-1
10
1
Ge/Si = 3 nm/3 nm
VDS= 0.01 V
Channel Area: 1μm X 1 μm
IDS (μA)
Gate Voltage (V)
Tox=2 nm
Tox=3 nm
Fig. 5. Two simulated voltage sweeping measurements of source-to-drain
current as a function of the gate voltage. The tunneling oxide thicknesses
for the two curves are 2 and 3 nm, respectively. The Ge/Si dot size is 3 nm/
3 nm. The sweep speed is 0.2 V/s.
D. Zhao et al. / Solid-State Electronics 50 (2006) 362–366
365

Page 5

a defect-free Si NC memory with the same dot size (8 nm)
and tunneling oxide thickness possess an extremely short
retention time, in the order of 1 s, as shown in the inset
of Fig. 6. However, the retention is in the order of 106s
for a Ge/Si HNC memory, despite influence of the dot size,
showing the evident advantage of using Ge/Si HNCs to
replace Si NCs for future flash memory.
4. Conclusion
The dynamic transient processes for Ge/Si hetero-nano-
crystal flash memory devices are simulated. The influences
of Ge/Si dot size, tunneling oxide thickness and gate volt-
age on writing, erasing and retention transient characteris-
tics are investigated. Compared with a Si nanocrystal
memory, a Ge/Si hetero-nanocrystal improves the reten-
tion characteristics dramatically without significantly influ-
encing
nanocrystal memory shows a weaker writing saturation
feature than a Si nanocrystal memory. Almost exactly the
same erasure performance is found for Ge/Si hetero-nano-
crystal memory and Si nanocrystal memory if the erasing
voltage is the same. Therefore, a Ge/Si hetero-nanocrystal
memory can replace a Si nanocrystal memory and the scal-
ing-down process of flash memory can be continued.
the writing/erasingspeed.AGe/Si hetero-
Acknowledgements
The authors acknowledge the financial and program
support of the Microelectronics Advanced Research Cor-
poration (MARCO) and its Focus Center on Function
Engineered NanoArchitectonics (FENA).
References
[1] Tiwari S, Rana F, Chan K, Hanafi H, Chan W, Buchanan D. Appl
Phys Lett 1996;68:1377–9.
[2] Nakajima A, Futatsugi T, Kosemura K, Fukano T, Yokoyama N.
Appl Phys Lett 1997;70:1742–4.
[3] Shi Y,SaitoK,Ishikuro H,
1998;84:2358–60.
[4] Shi Y, Saito K, Ishikuro H, Hiramoto T. Jpn J Appl Phys
1999;38:2453–6.
[5] Saitoh M, Nagata E, Hiramoto T. Appl Phys Lett 2003;82:1787–9.
[6] She M, King TJ. IEEE Trans Electron Dev 2003;50:1934–40.
[7] Yang HG, Shi Y, Pu L, Gu SL, Shen B, Han P, et al. Microelectron J
2003;34:71–5.
[8] Zhu Y, Zhao DT, Li RG, Liu JL. J Appl Phys 2005;97:034309.
[9] Ando Y, Itoh T. J Appl Phys 1987;61:1497–502.
[10] Yang WW, Cheng XH, Xing YM, Li WJ, Yu YH. J Appl Phys
2003;94:4032–5.
[11] Register LF, Rosenbaum E, Yang K. Appl Phys Lett 1999;74:457–9.
[12] Weinberg ZA. J Appl Phys 1982;53:5052–6.
[13] Paul SFP, Fouckhardt H. Phys Lett A 2001;286:199–204.
HiramotoT.J ApplPhys
/cm2
Charge Density (1011 q0
ensity
Chqrge D
0
TOX=2 nm
0246810
0.1
1
10
)
Time (x106s)
Ge/Si
5 nm/5 nm
4 nm/4 nm
3 nm/3 nm
Tox=2 nm
0.00.4
Time (s)
0.81.21.6
0.1
1.0
10.0
(10
11 q /cm
2)
Si Dot: 8 nm
Fig. 6. Charge retention transients of Ge/Si hetero-nanocrystal memories
with different Ge/Si dot sizes. The inset is the time-dependent charge in the
Si nanocrystal memory. The tunneling oxide is 2.0 nm for all the devices.
366
D. Zhao et al. / Solid-State Electronics 50 (2006) 362–366