Auxiliary qubit selection: a physical synthesis technique for quantum circuits

Quantum Information Processing (Impact Factor: 1.92). 04/2011; 10(2):139-154. DOI: 10.1007/s11128-010-0183-0

ABSTRACT Quantum circuit design flow consists of two main tasks: synthesis and physical design. Addressing the limitations imposed
on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design
processes, we introduced the concept of “physical synthesis” for quantum circuit flow and proposed a technique for it. Following
that concept, in this paper we propose a new technique for physical synthesis using auxiliary qubit selection to improve the
latency of quantum circuits. Moreover, it will be shown that the auxiliary qubit selection technique can be seamlessly integrated
into the previously introduced physical synthesis flow. Our experimental results show that the proposed technique decreases
the average latency objective of quantum circuits by about 11% for the attempted benchmarks.

KeywordsQuantum computing–Physical design–Physical synthesis–Auxiliary qubit selection

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Available from: Morteza Saheb Zamani, Apr 08, 2015
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    • "However, without interaction between the physical design and the synthesis processes the generated layout was not good. Addressing this issue, the physical synthesis [10] concept, the interaction between synthesis and physical design processes, was introduced in [11] and [12] for quantum circuits. The physical synthesis modifies the netlist or layout considering the layout information to improve the objectives (e.g. "
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    ABSTRACT: In our previous works, we have introduced the concept of "physical synthesis" as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging and auxiliary qubit selection) to demonstrate the effectiveness of the physical synthesis. However, the previous contributions focused mainly on the physical synthesis concept, and the techniques were proposed only as a proof of concept. In this paper, we propose a methodological framework for physical synthesis that involves all previously proposed techniques along with a newly introduced one (called auxiliary qubit insertion). We will show that the entire flow can be seen as one monolithic methodology. The proposed methodology is analyzed using a large set of benchmarks. Experimental results show that the proposed methodology decreases the average latency of quantum circuits by about 36.81 % for the attempted benchmarks.
    Quantum Information Processing 02/2014; 13(2):445-465. DOI:10.1007/s11128-013-0661-2 · 1.92 Impact Factor
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    ABSTRACT: Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming (ILP) regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11% for a set of attempted benchmarks and by about 9% for another set of benchmarks compared with the best in literature.
    Quantum Information Processing 06/2013; 12(10). DOI:10.1007/s11128-013-0597-6 · 1.92 Impact Factor
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    ABSTRACT: This paper presents a physical mapping tool for quantum circuits, which generates the optimal universal logic block (ULB) that can, on average, perform any logical fault-tolerant (FT) quantum operations with the minimum latency. The operation scheduling, placement, and qubit routing problems tackled by the quantum physical mapper are highly dependent on one another. More precisely, the scheduling solution affects the quality of the achievable placement solution due to resource pressures that may be created as a result of operation scheduling, whereas the operation placement and qubit routing solutions influence the scheduling solution due to resulting distances between predecessor and current operations, which in turn determines routing latencies. The proposed flow for the quantum physical mapper captures these dependencies by applying (1) a loose scheduling step, which transforms an initial quantum data flow graph into one that explicitly captures the no-cloning theorem of the quantum computing and then performs instruction scheduling based on a modified force-directed scheduling approach to minimize the resource contention and quantum circuit latency, (2) a placement step, which uses timing-driven instruction placement to minimize the approximate routing latencies while making iterative calls to the aforesaid force-directed scheduler to correct scheduling levels of quantum operations as needed, and (3) a routing step that finds dynamic values of routing latencies for the qubits. In addition to the quantum physical mapper, an approach is presented to determine the single best ULB size for a target quantum circuit by examining the latency of different FT quantum operations mapped onto different ULB sizes and using information about the occurrence frequency of operations on critical paths of the target quantum algorithm to weigh these latencies. Experimental results show an average latency reduction of about 40 % compared to previous work.
    Quantum Information Processing 12/2013; 13(5). DOI:10.1007/s11128-013-0725-3 · 1.92 Impact Factor