Auxiliary qubit selection: A physical synthesis technique for quantum circuits

Quantum Information Processing (Impact Factor: 1.92). 04/2011; 10(2):139-154. DOI: 10.1007/s11128-010-0183-0


Quantum circuit design flow consists of two main tasks: synthesis and physical design. Addressing the limitations imposed
on optimization of the quantum circuit objectives because of no information sharing between synthesis and physical design
processes, we introduced the concept of “physical synthesis” for quantum circuit flow and proposed a technique for it. Following
that concept, in this paper we propose a new technique for physical synthesis using auxiliary qubit selection to improve the
latency of quantum circuits. Moreover, it will be shown that the auxiliary qubit selection technique can be seamlessly integrated
into the previously introduced physical synthesis flow. Our experimental results show that the proposed technique decreases
the average latency objective of quantum circuits by about 11% for the attempted benchmarks.

KeywordsQuantum computing–Physical design–Physical synthesis–Auxiliary qubit selection


Available from: Morteza Saheb Zamani, Apr 08, 2015
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    • "However, without interaction between the physical design and the synthesis processes the generated layout was not good. Addressing this issue, the physical synthesis [10] concept, the interaction between synthesis and physical design processes, was introduced in [11] and [12] for quantum circuits. The physical synthesis modifies the netlist or layout considering the layout information to improve the objectives (e.g. "
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    ABSTRACT: In our previous works, we have introduced the concept of "physical synthesis" as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging and auxiliary qubit selection) to demonstrate the effectiveness of the physical synthesis. However, the previous contributions focused mainly on the physical synthesis concept, and the techniques were proposed only as a proof of concept. In this paper, we propose a methodological framework for physical synthesis that involves all previously proposed techniques along with a newly introduced one (called auxiliary qubit insertion). We will show that the entire flow can be seen as one monolithic methodology. The proposed methodology is analyzed using a large set of benchmarks. Experimental results show that the proposed methodology decreases the average latency of quantum circuits by about 36.81 % for the attempted benchmarks.
    Quantum Information Processing 02/2014; 13(2):445-465. DOI:10.1007/s11128-013-0661-2 · 1.92 Impact Factor
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    ABSTRACT: Quantum circuit design flow consists of two main tasks: synthesis and physical design. Synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netlist, produces the layout, and schedules the netlist on the layout. Quantum physical design problem is intractable. This process can be divided into two main processes: scheduling and layout generation. Some heuristic techniques have been proposed for the layout generation. These techniques do not produce good layouts for large netlists in terms of latency. Focusing on this issue, in this paper, a hierarchical layout generation algorithm is proposed that generates better layouts in terms of latency. Ion trap is used as the underlying technology in this paper. Experimental results show that the proposed algorithm decreases the average latency of quantum circuits by about 22% for the attempted benchmarks.
    Computer Architecture and Digital Systems (CADS), 2013 17th CSI International Symposium on; 01/2013
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    ABSTRACT: Implementing large-scale quantum circuits is one of the challenges of quantum computing. One of the central challenges of accurately modeling the architecture of these circuits is to schedule a quantum application and generate the layout while taking into account the cost of communications and classical resources as well as the maximum exploitable parallelism. In this paper, we present and evaluate a design flow for arbitrary quantum circuits in ion trap technology. Our design flow consists of two parts. First, a scheduler takes a description of a circuit and finds the best order for the execution of its quantum gates using integer linear programming (ILP) regarding the classical resources (qubits) and instruction dependencies. Then a layout generator receives the schedule produced by the scheduler and generates a layout for this circuit using a graph-drawing algorithm. Our experimental results show that the proposed flow decreases the average latency of quantum circuits by about 11% for a set of attempted benchmarks and by about 9% for another set of benchmarks compared with the best in literature.
    Quantum Information Processing 06/2013; 12(10). DOI:10.1007/s11128-013-0597-6 · 1.92 Impact Factor
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