Chapter

Modeling of CSP, KPN and SR Systems with SystemC

DOI: 10.1007/1-4020-7991-5_9
Source: DBLP

ABSTRACT In this chapter we show the ability to specify with SystemC under the restrictions imposed by several model of computations,
namely CSP, KPN and SR. Specifying under these MoCs provides some important properties, specially determinism and more protection
against blocking, which are also important when implementation process is faced. In most cases, standard primitive SystemC
channels or a combined use of them is suitable for specifying under these MoC restrictions. Nevertheless we provide some new
specific and compatible channels providing important features, as dynamic checking of restrictions or atomic use. These channels
represent an extension of the standard SystemC library.

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Available from: Eugenio Villar, Feb 18, 2015
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    • "Also the seminal SystemC reference [5] mentions Kahn Process Networks. Modeling Kahn Process Networks, CSP and Synchronous Reactive systems in SystemC is also explored in [6]. Heterogeneous modeling in SystemC is addressed in [12], [17]. "
    Workshop on Model Based Engineering for Embedded Systems Design (M-BED 2011); 03/2011
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    • "Beside the modeling and design space exploration aspects , there are several approaches to efficiently represent MoCs in SystemC. The facilities for implementing MoCs in SystemC have been extended by Herrera et al. [25] who have implemented a custom library of channel types like rendezvous on top of the SystemC discrete event simulation kernel . But no constraints have imposed how these new channel types are used by an actor. "
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    ABSTRACT: Digital signal processing algorithms are of big importance in many embedded systems. Due to complexity reasons and due to the restrictions imposed on the implementations, new design methodologies are needed. In this paper, we present a SystemC-based solution supporting automatic design space exploration, automatic performance evaluation, as well as automatic system generation for mixed hardware/software solutions mapped onto FPGA-based platforms. Our proposed hardware/software codesign approach is based on a SystemC-based library called SysteMoC that permits the expression of different models of computation well known in the domain of digital signal processing. It combines the advantages of executability and analyzability of many important models of computation that can be expressed in SysteMoC. We will use the example of an MPEG-4 decoder throughout this paper to introduce our novel methodology. Results from a five-dimensional design space exploration and from automatically mapping parts of the MPEG-4 decoder onto a Xilinx FPGA platform will demonstrate the effectiveness of our approach.
    EURASIP Journal on Embedded Systems 01/2007; 2007(1). DOI:10.1155/2007/47580
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    • "Beside the modeling and design space exploration aspects , there are several approaches to efficiently represent MoCs in SystemC. The facilities for implementing MoCs in SystemC have been extended by Herrera et al. [25] who have implemented a custom library of channel types like rendezvous on top of the SystemC discrete event simulation kernel . But no constraints have imposed how these new channel types are used by an actor. "
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