IEICE TRANS. ELECTRON., VOL.E89–C, NO.4 APRIL 2006
Accurate Small-Signal Modeling of FD-SOI MOSFETs
Special Section on Advanced RF Technologies for Compact Wireless Equipment and Mobile Phones
Guechol KIM†a), Nonmember, Yoshiyuki SHIMIZU†, Student Member, Bunsei MURAKAMI†, Masaru GOTO†,
Keisuke UEDA†, Takao KIHARA†, Nonmembers, Toshimasa MATSUOKA†, and Kenji TANIGUCHI†, Members
insulator (FD-SOI) MOSFETs operating at RF frequencies is presented.
The model accounts for the non-quasi-static effect by determining model
parameters using a curve fitting procedure to reproduce the frequency re-
sponse of FD-SOI MOSFETs. The accuracy of the model is validated
by comparison of S parameters with measured results in the range from
0.2GHz to 20GHz.
key words: FD-SOI, MOSFET, RF, modeling, non-quasi-static
A new small-signal model for fully depleted silicon-on-
MOSFETs with a fully depleted silicon-on-insulator (FD-
SOI) structure have lower substrate capacitance compared
to bulk MOSFETs and as such are advantageous for high-
frequency circuits ,. However, short-channel FD-SOI
devices operating in the linear region exhibit a relatively
long delay in drain conductance as a non-quasi static (NQS)
effect ,. Although the parameters of conventional
quasi-static models are usually determined from the mea-
suredS parameters usingseveraldirectmethods, suchmeth-
ods are not applicable for NQS models due to the large num-
ber of unknown parameters. In this paper, a new FD-SOI
MOSFET model is proposed in which the parameters are
accurately determined for RF operation by curve fitting to
experimental results in such a way as to reduce the uncer-
tainty of the model parameters, including NQS channel re-
sistances (Rgsiand Rgdi) and drain current response times
2. Experimental Results and Discussion
n-MOSFETs with multiple n+poly-gate fingers (0.14µm
length by 5µm width per finger) were fabricated on high-
resistivity SOI wafers using a 0.15µm FD-SOI CMOS pro-
cess. A both-side gate connection structure was used in or-
der to reduce gate resistance. The S parameters were mea-
sured with the source and substrate terminals grounded and
the body terminal open. Pad and interconnection parasitics
were removed from the measured S parameters by applying
a de-embedding procedure using open and short test pat-
terns. Figure 1 shows a widely used small-signal equivalent
Manuscript received August 30, 2005.
Manuscript revised November 25, 2005.
†The authors are with the Graduate School of Engineering,
Osaka University, Suita-shi, 565-0871 Japan.
Conventional small-signal equivalent circuit for an RF MOSFET.
circuit for an RF MOSFET . The measured Y param-
eters for an FD-SOI MOSFET with W = 5 × 48µm and
L = 0.14µm (VGS = 1.0 V, VDS = 0.2 V) are shown in
To illustrate the drawbacks of the conventional model,
Y parameters determined by the conventional are compared
with those for the new models and measured results in
Fig.2. Re(Y11) andRe(Y21) givenby the conventional model
deviate substantially from the measured results at frequen-
cies higher than 5GHz. This discrepancy is attributable to
the NQS effect, by which the speed of channel charge is
limited due to the finite channel conductance produced by
every infinitesimal gate-channel capacitor along the channel
. As shown in Fig.3, this effect can be explained by the
NQS channel resistances (Rgsiand Rgdi) coupled to the gate-
source, gate-drain capacitances, and resulting delay of gm,
as described by
1 + jωτgm
where gm0is the low-frequency transconductance and τgm
is the drain current response time for vgs. Similar modeling
has been investigated in other FETs . The delay of gm
also contributes transcapacitance (Cm) .
In addition, Y22 derived by the conventional equiva-
lent circuit increases with frequency in both Re(Y22) and
Im(Y22). However, as shown in Fig.2, the short-channel
SOI-MOSFETs measured at VDS = 0.2 V exhibit a small
decrease in Re(Y22) over 5GHz, and a noticeable decrease
with frequency in Im(Y22). The differences between the
measured results and the conventional analytical frequency
dependence originate from the delay of the drain current re-
sponse. For bulk devices, the existence of large drain para-
sitic capacitances causes appreciable suppression of the fre-
quency dependence caused by the delay of the drain current
response. The intrinsic delay of gdscan be simulated by in-
troducing the frequency dependence of gds, as given by 
Copyright c ? 2006 The Institute of Electronics, Information and Communication Engineers
IEICE TRANS. ELECTRON., VOL.E89–C, NO.4 APRIL 2006
48µm, L = 0.14µm, VGS=1.0V, VDS=0.2V)
Comparison of Y parameters for FD-SOI MOSFETs. (W = 5 ×
Proposed RF small-signal equivalent circuit for FD-SOI MOS-
1 + jωτgds
where gds0is the low-frequency drain conductance and τgds
is the drain current response time. The real part of Eq.(2)
decreases at high frequency, and the imaginary part with
negative sign decreases with increasing frequency, which
explains the frequency dependence of the proposed model
including the delay of gds, as seen in Y22(Fig.2).
Althoughsome partsof Fig.3maynot bemodeledwith
sufficient accuracy by the compact models used in current
circuit simulators, those parts may be readily implemented
as external components to be added to the compact MOS
model in macro or subcircuit model techniques .
3. Model Parameter Extraction
The values of Y22calculated by the proposed model, which
accounts for the delay, indicate that short-channel FD-SOI
devices exhibit drain current response delay, even in the
saturation region . Accurate model parameters that are
capable of reproducing the small-signal response of FD-
SOI MOSFETs in both the linear and saturation regions are
therefore necessary. Figure 3 shows the proposed small-
signal model for FD-SOI MOSFETs including the NQS ef-
fect. The proposed model parameters are determined sep-
arately on the input and output sides. The poly-gate re-
sistance (Rg) and NQS channel resistances (Rgsiand Rgdi)
must be determined separately due to the irregular geometry
and bias dependence of the effective gate resistance result-
ing from the combined distributed effects in both the gate
and channel at high frequency .
In the first step, the input-side parameters for the pro-
posed model (Cgs, Cgd, Rg, Rgsi, Rgdi) are determined. Cgs
and Cgdcan be obtained from the measured results as fol-
Cgs= (Im(Y11) + Im(Y12))/ω
Rgcan be found by reducing the fitting parameter, i.e.,
where Rsgis the sheet resistance of gate polysilicon, Wf is
the gate width per finger, Lf is the gate length, and Nf is
the number of gate fingers. Rgsiand Rgdiare determined by
In the second step, the output-side parameters for the
proposed model (gm0, gds0, τgds, τgm) are determined. Here,
gm0and gds0are also derived from the measured results, as
Similarly, τgdsand τgmare determined by curve fitting. In
this study, Csuband Rsubin Fig.3 are neglected, due to low
L = 0.14µm in the linear and saturation regions.
Measured and modeled S parameters with W = 5 × 48µm and
various bias conditions.
Extracted parametersfor a5×48µm/0.14µmMOSdeviceunder
drain-source and drain-body capacitances. Figure 4 shows
the measured S parameters and the results obtained by the
proposed small-signal model with the parameters listed in
Table 1. This figure demonstrates good agreement between
the measured and modeled S parameter up to 20GHz.
Short-channel FD-SOI MOS devices operating in the lin-
ear region exhibit substantial drain current response delay
due to the small parasitic capacitance in such devices. To
explain this phenomenon, an accurate small-signal model
for FD-SOI MOSFETs operating at high frequency was pre-
sented. The model parameters attributed to the NQS effect
are accurately determined by curve fitting. The validity of
the proposed model was demonstrated by comparison of S
parameters with measured results at up to 20GHz.
This work was supported by the Semiconductor Technology
Academic Research Center (STARC).
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