Article

# Accurate Small-Signal Modeling of FD-SOI MOSFETs

IEICE Transactions on Electronics (Impact Factor: 0.33). 04/2006; E89-C(4):517-519. DOI: 10.1093/ietele/e89-c.4.517

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**ABSTRACT:**An RF small-signal and noise model of fully depleted silicon-on-insulator (FD-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is presented. The model together with its intrinsic model parameters extracted from de-embedding extrinsic parameters reproduces the frequency and noise response of FD-SOI MOSFETs. We have applied the proposed model to a low-noise amplifier (LNA) operating at 5.5 GHz, which is implemented in a 0.15 mum FD-SOI complementary metal-oxide-semiconductor (CMOS) technology. The simulated small-signal and noise performance of the LNA are in good agreement with the measured data of the fabricated LNA.Japanese Journal of Applied Physics 09/2006; 45(9A):6872-6877. · 1.06 Impact Factor - [Show abstract] [Hide abstract]

**ABSTRACT:**In this paper, we propose a new method for the bias-dependent parameter extraction of a MOSFET, which covers DC to over 100GHz. The DC MOSFET model provided by the chip foundry is assumed to be correct, and the core DC characteristics are designed to be asymptotically recovered at low frequencies. This is carried out by representing the corrections required at high frequencies using a bias-dependent Y matrix, assuming that a parasitic nonlinear two-port matrix (Y-wrapper) is connected in parallel with the core MOSFET. The Y-wrapper can also handle the nonreciprocity of the parasitic components, that is, the asymmetry of the Y matrix. The reliability of the Y-wrapper model is confirmed through the simulation and measurement of a one-stage common-source amplifier operating at several bias points. This paper will not discuss about non-linearity.IEICE Transactions on Electronics 01/2012; E95.C(6):1077-1085. · 0.39 Impact Factor - [Show abstract] [Hide abstract]

**ABSTRACT:**A highly efficient and accurate extraction algorithm for the small-signal equivalent-circuit parameters of a GaN high electron-mobility transistor device is presented. Elements of the extrinsic equivalent-circuit topology are evaluated using a modified "cold field-effect transistor" approach whereby the undesirable need to forward bias the device's gate terminal is avoided. Intrinsic elements are determined based on a circuit topology, which identifies, for the first time, a time delay in the output conductance of GaN-based devices. The validity of the proposed algorithm has been thoroughly verified with excellent correlation between the measured and modeled S-parameters up to 50 GHz.IEEE Transactions on Microwave Theory and Techniques 08/2008; · 2.94 Impact Factor

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