A five-transistor bandpass filter element

Abstract

This paper explores a five-transistor continuous-time band-pass filter element called the capacitively coupled current conveyor (C⁴) with a programmable pass-band. We show measurement data from 1Hz to 100kHz. This paper discusses the effects of various design parameters on frequency-range, gain and linearity. Experimental data is presented from circuits fabricated on a 0.5μm nwell CMOS process available through MOSIS.

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A FIVE-TRANSISTOR BANDPASS FILTER ELEMENT
Paul D. Smith, David W. Graham, Ravi Chawla and Paul Hasler∗
Georgia Institute of Technology
Department of Electrical and Computer Engineering
Atlanta, GA 30332
ABSTRACT
This paper explores a five-transistor continuous-time band-pass
filter element called the Capacitively Coupled Current Conveyer
(C4) with a programmable pass-band. We show measurement data
from 1Hz to 100kHz . This paper discusses the effects of various
design parameters on frequency-range, gain and linearity. Experi-
mental data is presented from circuits fabricated on a 0.5µm nwell
CMOS process available through MOSIS.
Band-pass filter elements have a long history, from sim-
ple linear-systems to standard implementations [1]. The
mainusebeingsomeformofsignaldecomposition, whether
it be to amplify/attenuate a specific signal frequency, or to
separate multiple frequencies [2, 3, 4]. Tuning of these de-
vices is critical [5, 6], in addition to matching, power, and
overall die area. The filter discussed in this paper has a
simple topology (5 transistors), uses a single power-supply,
uses very little power, and is easily tunable. It will also
serve as a good starting point for developing higher order
bandpass filters.
The initial theory on the capacitively coupled cur-
rent conveyer (C4) was developed from the Autozeroing
Floating-Gate Amplifier (AFGA) [7], which had widely
separated corner frequencies due to limitations of the de-
vice. The C4is a capacitively based bandpass filter that
models the tunneling and the hot-electron injection with
transistors, thus removing the corner frequency limitations.
The circuit is shown in Fig. 1. This circuit has previously
been used in many systems [8, 4], but these applications
were designed with very low Q’s, typically less than 1. Such
low values of Q will not work for some applications, one ex-
ample of this would be a cochlea stage which requires Q’s
as high as 30 for low amplitude signals. In designing sys-
tems with moderate to high Q’s there are certain properties
that will play a significant role. Within this paper, we hope
to cover these issues to clarify the design and use of the C4
within these systems.
∗This work was partially supported by grants National Science Foun-
dation ( CISE-1068549, ECS (CAREER): 0093915, ECS-9988905) and
by corportate donations to the Georgia Tech Analog Consortium by Texas
Instruments and Motorola, Inc.
Vτl
Vτh
C2
Vin
Vout
CL
C1
CW
Vdibl
M2
M3
M4
M1
Fig. 1. Schematic of a single C4structure. The capacitors model all
explicit and parasitic capacitances in the signal path of the circuit.
1. FREQUENCY TUNING
The C4’s corner frequencies are electronically tunable and
can be set independently of one another. The frequency re-
sponse of the C4is governed by
Vout
Vin
= −C1
C2
sτl(1 − sτf)
s2τhτl+ s(τl+ τf(Co
κC2− 1)) + 1
(1)
where the time constants are given by
τl=C2UT
κIτl
τf=C2UT
κIτh
UT
κIτh
τh=CTCO− C2
2
C2
UT is the thermal voltage (25.9mV @25oC) and κ is the
subthreshold slope. The total capacitance, CT, and the out-
put capacitance, CO, are defined as CT = C1+ C2+ CW
and CO= C2+ CL. The currents Iτland Iτhare the cur-
rents through M2and M3, respectively in Fig. 1. With nor-
mal usage, τfis so fast that the zero it produces lies far out-
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Fig. 2. C4frequency response curves. (a) Frequency response curve for a C4with a gain of 5. Showing that each corner frequency can move independently.
(b) Unity gain C4showing tunability over a wide range of frequencies. (c) The Q for a C4can also be tuned, up to the maximum theoretical Q. (d) C4
change in gain with C2. Data similar to earlier work [8].
side of the operating range. The plots of Fig. 2 show mea-
sured data from a 0.5µm process available through MOSIS
that summarizes the frequency response of the C4.
The C4takes on the properties of a bandpass filter with
first-order roll-off and a pass-band gain set by the ratio of
the two coupling capacitors as Av= −C1/C2. The overlap
capacitance of the MOSFET causes there to always be some
effective C2capacitance, even if it is only a few fF, so the
gain is not infinite. The overall time constant of the filter,
which gives the center frequency, is
τ =√τlτh
(2)
Furthermore, since the corner frequencies of the C4are
completely independent of each other, as shown in Fig.2a,
either one of the corner frequencies could be pulled to the
extreme allowing the C4to take the form of a lowpass or
highpass filter.
2. DESIGNING FOR Q
By tuning the filter such that τh> τl, resonance occurs, and
the value of the Q peak is
?
C2
2
Q =
CTCO− C2
2
x
1 + x2?
?Iτl
CO
κC2− 1
?
(3)
where
x =
Iτh
(4)
Fig. 3 is a plot of the Q peak versus the ratio of Iτl/Iτhfor a
unity-gain C4using the extracted values of the capacitances
from the layout. As can be seen from this MATLAB plot,
there is a maximum value that the resonance can achieve.
The maximum value occurs when Iτhis slightly larger than
Iτlfor the capacitances of the fabricated circuit that yielded
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Fig. 3. Q as a function of Iτh/Iτl. There is a maximum Q at a particular
current ratio, and the curve is relatively flat around that maximum point.
The maximum achievable Q for this circuit was designed to be approxi-
mately 1. Higher maximum values of Q can be explicitly designed into the
circuit.
the plots of Fig. 3. The maximum value of the Q peak can
be predicted for a certain set of capacitances by taking the
derivative of (3) and finding the maximum, and this is given
by
?
C2(CO− κC2)
1
2
C2
Qmax
=
1
2
κ(CTCO− C2
2)
(5)
≈
?
κ(C1+ CW)
for C2? CO
(6)
This represents the maximum Q for small amplitudes and
will drop as amplitude increases. This phenomena is not
discussed within the scope of this paper, but will be dis-
cussed later. As can be seen from Fig. 3, the C4was not
designed to have a large Q peak. However, by changing the
capacitances, a much larger Q peak can be achieved. For ex-
ample, by reducing the value of C2, more resonance occurs.
A good method to increase Q is to not explicitly draw any
C2capacitance and use the gate-drain overlap capacitance
of M4 in Fig. 1 as C2.
3. DESIGNING FOR MULTIPLE FILTER STAGES
One potentially hazardous trait of the C4is that the input
capacitance of the circuit does not necessarily remain con-
stant, but it varies based on frequency. This is particularly
critical when cascading multiple C4stages to create higher
order filter banks. If the previous stage in the overall sys-
tem is dependant upon the input capacitance of the C4for
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Fig. 4. Change in C4input capacitance vs. frequency. Low frequency
input capacitance = C1. This transitions to the high-frequency input ca-
pacitance which is roughly C1//Cw.
its load capacitance, then this could be a serious issue.
Referring back to Fig.
easily be found for the cases of very low frequencies and
very high frequencies. For very low frequencies, the middle
node is an AC ground because of the high-gain amplifier.
Hence, the input capacitance for low frequencies is simply
Cin = C1. For very high frequencies, the transistors can
no longer follow the signals, so the C4reduces to a net-
work of capacitors and the input capacitance becomes the
series/parallel combination of the capacitances in this net-
workseenlookingintotheinput, Vin. Theinputcapacitance
for the two extreme cases are given by
1, the input capacitance can
Cin(f → 0) = C1
Cin(f → inf) = C1?(CW+ C2?CL) ≈ C1?CW (7)
There is a transition region for the input capacitance be-
tween these states which occurs over a confined frequency
band near the center frequency of the C4. Fig. 4 shows re-
sults of a SPICE simulation in which the input capacitance
was computed. Simulation and experiments closely agree
for this circuit.
However, since the width of the swing in input capac-
itance is a function of the values of the capacitances, the
effect of the input-capacitance shift can be minimized with
a judicious choice of capacitor values. Increasing the drawn
size of CW is the best choice for reducing the shifting in-
put capacitance for the simple reason that the larger the
value of CW, the more closely C1?CW ≈ C1, and hence
the more closely the high-frequency Cinapproaches the the
low-frequency Cin. Fig. 4 shows the results of 10-fold in-
creases in the capacitance of CW. The larger that CW is
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Vτl
Vτh
VDIBL
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Fig. 5. (a) C4change in linearity with DIBL voltage. The linear range
of a C4bandpass filter is improved by using source degeneration in the
feedback path. A DIBL transistor is chosen to provide an exponential rela-
tionship that is more flat than a regular transistor because of it’s very small
early voltage. For simplicity each curve is offset +500mV. The lower curve
shows the output when the DIBL voltage is closest to it’s ideal voltage. (b)
A circuit implementation toprovide a self-bias forthe DIBL transistor. The
optimal DIBL voltage would be determined by the bias point of a given C4,
therefore a separate circuit would be required for each filter.
drawn, the less the effect of the input capacitance shift on
the system.
Another way of reducing the effects of the shifting in-
put capacitance is to put a buffer in front of the C4so that
the previous circuit always sees the same load capacitance.
However, for many cases, spending the real estate required
for a buffer could be better used by simply increasing the
size of the CW capacitor because increasing CW has ad-
vantages besides keeping Cinrelatively fixed. The primary
reason that CWis drawn in the C4is to capacitively divide
the input signal and thus increase the input linear range.
4. DECREASING DISTORTION
The C4uses a short-channel device, named a DIBL (Drain-
Induced Barrier Loading) transistor, to decrease the loop-
gain in the feedback path and increase the overall linearity
of the device. A DIBL transistor is chosen to provide an
exponential relationship that is more flat than a regular tran-
sistor because of it’s very small early voltage. During initial
characterization this device has it’s gate pulled to VDD in
order to remove it from the loop, however, an optimal bias
point for the device is shown to improve linearity. Fig. 5(a)
shows the decrease in the second harmonic as the DIBL bias
approaches it’s optimal value. The optimal DIBL voltage is
dependent on the DC operating point, which changes with
corner frequency for each filter. Fig. 5(b) shows a self-
biasing scheme that is currently being testing to work over
all frequencies thus increasing linearity without external bi-
ases. Inthecaseofanarrayofthesedevices, theself-biasing
DIBL circuitry would be required for each filter tap because
VDIBLis dependent upon Vτland Vτh, which change de-
pending on the frequency response of the individual filter.
5. CONCLUSION
In this paper we have shown the design parameters which
affect frequency response, gain and linearity of a 5 transis-
tor filter element. We have shown primarily experimental
results, along with some simulation, to verify the tunabil-
ity and linearity of the device. Taking all of these into ac-
count, this ultimately results in a low-power and compact
filter which can be easily tuned over 6 orders of magnitude
in frequencies with maximum Q factors that can explicitly
designed into a single stage. Using these design parameters,
one can begin to design higher-order C4filter banks, with
applications in numerous signal processing applications.
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