A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switched-current and continuous-time ΣΔ modulators

Abstract

This paper describes how to extend the capabilities of SIMULINK for the time-domain simulation of ΣΔ modulators implemented by using switched-capacitor, switched-current and continuous-time circuits, considering the most important error mechanisms. The behavioural models of these circuits are incorporated into the SIMULINK environment by using C-language S-function blocks, which leads to a drastic saving in the simulation time as compared to previous approaches based on MATLAB functions. The outcome is a complete SIMULINK block library that allows interactive, fast and accurate simulation of an arbitrary ΣΔ topology.

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A SIMULINK-BASED APPROACH
SWITCHED-CAPACITOR, SWITCHED-CURRENT AND CONTINUOUS-TIME
FOR FAST AND PRECISE SIMULATION OF
EA MODULATORS
Javier Moreno-Reina, Jost2 M. de la Rosa, Fernando Medeiro, Rafael Romay, Rocio del Rio, Bel& Pkrez- Verdu
and Angel Rodriguez- Vazquez
Instituto de Microelectronica de Se villa, IMSE-CNM (CSIC)
Edif. CNM-CICA, Avda. Reina Mercedes s/n, 4 1012 Sevilla, SPAIN
Phone: +34 95056666, FAX: +34 95056686, E-mail: jrosa@imse.cnm.es
ABSTRACT
This paper describes how to extend the capabilities of SIMULINK
for the time-domain simulation of ZA modulators implemented by
using switched-capacitor, switched-current and continuous-time
circuits. considering the most important error mechanisms. The
behavioural models of these circuits are incorporated into the
SIMULINK environment by using C-language S-function blocks,
which leads to a drastic saving in the simulation time as compared
to previous approaches based on MATLAB functions. The out-
come is a complete SIMULINK block library that allows interac-
tive, fast and accurate simulation of an arbitrary ZA topology (*I.
1. INTRODUCTION
Simulation is a critical part of both the top-down synthesis and the
bottom-up verification of Integrated Circuits (ICs). Thus, the iter-
ative use of simulators helps designers to explore the design space
and to optimize critical trade-offs at different hierarchical levels
[I]. In the case of ZA Modulators (ZAMs), as a consequence of
their sampled-data nature, simulation has to be done in the
time-domain. However, transistor-level
SPICE-like simulators yield to excessively long CPU times - typ-
ically several days, or even weeks. The reason is that several thou-
sands clock cycles - with small numerical integration steps and
complex models- are needed to obtain a realistic evaluation [2].
To overcome this 'problem, different alternatives for the simula-
tion of ZAMs have been proposed, which at the price of losing ac-
curacy in their models, reduce the simulation time [2][3][4]. One
of the best accuracy-speed trade-off is achieved by using the
so-called behavioural simulation technique [ 11. In this approach
the modulator is broken up into a set of subcircuits, often called
building blocks, which are described by explicit equations that re-
late the outputs in terms of the inputs and the intemal state varia-
bles. Thus, the accuracy of the simulation depends on how pre-
cisely those equations describe the real behaviour of each block.
In case of Discrete-Time (DT) CAMS implemented with either
switched-capacitor (SC) [3] or switched-current (SI) circuits [5],
the value of signals is important only at specific time points.
Therefore, each building block is defined by a set of finite differ-
ence equations which describe its functionality, and the simulation
process consists of computing the node voltages and branch cur-
rents of the circuit consecutively in each clock phase. The out-
come is a drastic saving in CPU time - only a few seconds to eval-
uate an output spectrum. Recently, behavioural simulation has
been applied also to Continuous-Time (CT) CAMS [6]. In this
case, model equations are computed analytically instead of nu-
merically, leading to CPU times comparable with the DT case.
simulations with
"'This
2001-34283lTAMES-2 and the Spanish CICYT Project TIC2001-0929/ADAVERE.
work has been supported by the
EU ESPRIT IST Project
In spite of their good trade-off between precision and CPU-time,
previously reported behavioural simulators present several draw-
backs. On the one hand, there is a limited number of ZAM topolo-
gies that can be simulated, normally using only one circuit tech-
nique. On the other hand, except for [4], the user interface consists
of an input netlist with a dedicated syntax, while postprocessing is
performed by using commercial tools like MATLAB [7].
The above-mentioned problems can be overcome by implement-
ing the behavioural models in the SIMULINK environment [8].
The benefits are a friendly Graphical User interface (GUI), high
flexibility for the extension of the block library and huge signal
processing capabilities. Recently, a set of SIMULINK block mod-
els has been proposed for the behavioural simulation of SC ZAMs
[9]. However, it has two major constraints:
The block library is limited to SC circuits, using simple models
which do not include some important limitations like mismatch
and the non-linearities associated to the open-loop opamp DC
gain and capacitors. In addition, as models are implemented in
the Z-domain, the circuit behaviour during different clock
phases is not considered, thus leading to an imprecise model-
ling of some errors like the incomplete settling.
Block models are realized by using MATLAB functions. This
causes the MATLAB interpreter to be called at each time step,
slowing down the simulation time drastically [8]. This problem
is aggravated as the model complexity increases, yielding to
excessive CPU times as compared to C-written simulators.
This is true even using the SIMULINK accelerator [8].
This paper presents an interactive and flexible approach for a fast
time-domain behavioural simulation of Lowpass (LP) and Band-
Pass (BP) ZAMs implemented by using not only SC, but also SI
and CT circuits. In order to speed up the simulation, EA-blocks are
incorporated in SIMULINKtlas C-coded S-functions [IO]. As a
result the CPU-time for one 65536-point simulation of a DT/CT
ZAM is typically less than 5 secondst2, meaning only a few times
slower than C-written simulators, but up to 2 orders of magnitude
faster than using MATLAB functions as in [9].
2. DESCRIPTION OF THE XAM-BLOCK LIBRARY
The proposed SIMULINK ZAM-block library includes different
sublibraries which are classified according to the modulator hier-
archy level and the circuit technique. As an illustration, Fig.1
shows some of these sublibraries showing: SI memory cells,
SCCT integrators and resonators (used in BP-ZAMs), quantizers,
71. SIMULINK 5 and MATLAB 6.5 (release 13) were used.
t2. All simulations shown in this paper were done using an Intel Pentium
4 CPU@1.7GHz @256MB RAM PC.
0-7803-7761-3/03/$17.00 02003 IEEE
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Figure 1. Illustrating some blocks of the proposed SIMULINK CAM-block library.
and both 1 -bit and multi-bit (mb) Digital-to-Analog Converters
(DACs). There is also a sublibrary including the most usual archi-
tectures of both LP- and BP-CAMS using SC, SI and CT circuits.
For each building block, the CAM-block library provides models
with a different abstraction level. The purpose is twofold. First,
high level models are suited for system level simulations and ini-
tial transmission of specifications. Second, low level accurate
models, which takes into account main circuit parasitics, are suit-
ed for fine-tuning the specs transmission and circuit validation.
The main circuit non-idealities included in the integrators (and
resonators) are:
- SC circuits: finite open-loop opamp DC gain, incomplete set-
tling error, mismatch capacitor ratio error, thermal noise; and
main non-linear effects, namely: non-linear sampling
switch-on resistance, non-linear open-loop opamp DC gain,
slew rate and non-linear capacitors.
CT circuits: finite DC gain, integration time constant error,
slew rate, finite non-linear transconductance and thermal noise.
SI circuits: linear and non-linear gain error, finite output-input
conductance ratio error, charge injection error, incomplete set-
tling error, mismatch error and thermal noise.
Detailed descriptions of these errors as well as their behavioural
models - beyond the scope of this paper - can be found in [3],
[ 113 and [SI for SC, CT and SI circuits, respectively.
In addition to integrators and resonators, quantizer and DAC er-
rors have to be considered, specially in SC/SI cascade mb archi-
tectures and CT single-loop topologies. For this purpose, the fol-
:lowing circuit parasitics have been included:
s quantizers: offset, both deterministic and random hysteresis,
and in mb realizations, gain error and integral non-linearity.
single-bit and multi-bit DAG: offset, gain error and integral
non-linearity. In case of CT ZAh4s, a time delay is also included
in order to simulate the effect of excess loop delay [ 1 I].
The behavioural models of the above-mentioned errors have been
-coded in C language, and incorporated into the SIMULINK envi-
ronment through the so-called Sfunctions [lo]. These are special
purpose C source files which allow us to add C algorithms to
SIMULINK models. The outcome is a notable saving of simula-
tion time as compared to use MATLAB functions or M-files to
code the models, even when the accelerator utility is used [8].
In order to create an S-function associated to building blocks like
those shown in Fig. 1, the following steps have to be followed:
Create a C-coded S-function containing the behavioural
model. For this purpose, SIMULINK provides different S-func-
tion templates which can accommodate the C-coded model of
both DT and CT systems. These templates are composed of
several routines that perform different tasks required at each
simulation stage [IO]. Among the others, these tasks include:
variable initialization, computing output variables, updating
state variables, etc. Thus, programmers’ work simply consists
in placing the C-coded behavioural model in the different parts
of the template file. For illustration purposes, Fig. 2(a) shows
the behavioural modeling and some significant sections of the
S-function file associated to an SC integrator with non-linear
opamp DC gain - not included in [9]. It includes model param-
eters, clock phase diagram, model code, etc.
Compiling the CMEX--file S-function. This is done by using the
mex utility provided by MATLAB [IO]. The resulting object
files are dynamically linked into SIMULINK when needed.
Incorporating the model into the SIMULINK environment.
This is done by using the S-function block of the SIMULINK
libraries [8]. Fig.2(b) illustrates this process for the SC integra-
tor of Fig.2(a). A block diagram containing the S-function
block is created including the input/output pins. The dialogue
box is used to specify the name of the underlying S-function -
in this case intfescavnl. In addition, model parameters are also
included in this box. In order to facilitate the use of building
blocks, the user can insert the values of model parameters from
a dialogue box associated to the block.
3. SIMULATION EXAMPLES
An arbitrary modulator architecture can be defined by connecting
the building blocks available in the CAM-block library. This can
be done by using the SIMULINK Library browser as usual. Alter-
natively, the ZAM-block library can be browsed by using a dedi-
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-
Figure 2. Basic steps to incorporate a behavioural model in the EAM-block library: (a) S-function file. (b) S-function block.
cated GUI that allows the user to navigate in an easy way through
all the steps of the simulation and post-processing of results.
As an illustration of the capabilities of the ZAM-block library, this
section shows the impact of some circuit parasitics on the per-
formance of the following modulator architectures:
A CT (Gm-C) 2nd-order LP-CAM (CT 2nd-LPZAM).
- A SI 4th-order BP-ZAM (SI 4th-BPZAM).
*
A SC 2-1-1 cascade mb (3b) ZAM (SC 2-12mb).
Fig.3 shows the block diagram of these architectures in the
SIMULINK environment, including building blocks from the
CAM-block library.
0
3.1 CT 2nd-LPZAM example
In the example shown in Fig.3(a), an ideal I-bit quantizer was
used while the other blocks include the following parameters:
Gm-C integrators: finite DC gain, time-constant error, unity
0
Figure 3. Block diagram of the ZAM-libray examples. (a) CT
2nd-LPZAM. (b) SI 4th-BPZAM. (c) SC 2-1 mb.
gain frequency, slew rate, temperature and output-swing.
DAC: reference voltage and time delay.
In high-speed applications, the performance of the modulator can
be severely degraded by finite bandwidth and slew rate. These er-
rors cause an increase of both the in-band noise power and the
harmonic distortion. This is illustrated in the output spectrum of
Fij:.4(a), obtained by performing an Hanning-windowed
65536-point FFT to the output bit stream of Fig.3(a), with a
half-scale@lO-kHz input tone, when clocked at 20 MHz. This
sirnulation takes 3 seconds when the accelerator is used.
In addition to integrator dynamics, one of the most important lim-
iting factors arising in CT-ZAMs is the time delay between the
quantizer clock edge and DAC response. This delay, referred to as
excess loop delay, modifies the noise-shaping transfer functions,
and may eventually make CT-ZAMs unstable [ 1 13. Mathematical-
ly speaking, a complex analysis would be required to obtain the
stability condition that relates the loop delay, T ~ ,
with the clock
-20 .
-180
S G I d e a I
.
'
' ' ..''.''
I 0 '
-200
.
'
IO2
I 0 '
I o6
Yo7
I O '
Frequency (Hz)
0
I W
200
300
4Ml
5W 6W
700
800 9W
loo0
Timc (#clock pcriods)
Figure 4.
(a) Harmonic distortion caused by slew rate. (b) Effect of excess
loop delay on the transient response of the first integrator.
Performance degradation of a CT 2nd-LPZAM.
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period, T, . Instead of that, simulation-based analyses are normal-
ly used. As an illustration, Fig.4(b) shows the first integrator out-
put waveform for different values of the DAC time delay, show-
ing unstable behaviour for zd = 3 Ts/2 .
3.2 SI 4th-BPXAM example
The SI 4th-BPZAM shown in Fig.3(b) has been obtained by ap-
plying a LP-to-BP transformation (z-’ 4 - z - ~ ) to a 2nd-LPZAM.
As a consequence of this transformation, the zeroes of the noise
transfer function shift from DC to a quarter of the sampling fre-
quency, fs. In addition, the integrators in the original LP-CAM
become resonators. In this example, resonators are based on loss-
less direct integrators. Note that a front-end block, named SI buff-
er, is used to model the voltage-to-current conversion.
One of the most important degrading factors in SI BP-CAMS is the
signal-dependent transconductance of memory cells, g , , which
force all errors to be non-linear. As a consequence, in addition to
increase the in-band noise power, SI errors cause Interuodulation
-
Distortion (IMD). As an illustration, Fig.5 shows the impact of the
non-linear settling on the performance of the modulator in
Fig.3(b). In this case, the gate-source capacitance of memory tran-
sistors, CgS, is varied showing three effects: increase of the
in-band noise, third-order IMD and a shift of the quantization
noise-filtering notch frequency, Sf,. These output spectra are ob-
tained by running two 65536-point simulations of Fig.3(b), each
one taking 4 seconds.
3.3 sc 2 - 1 ~ ~ 6
In the case of SC CAMs, the behavioural models of building
blocks have been translated from ASIDES, a C-coded time-do-
main behavioural simulator for SC CAMs [3]. As a consequence
of this translation, simulation results obtained with both
SIMULINK and ASIDES are practically identical. Compared to
ASIDES, the proposed SIMULINK ZA-block library offers a
friendly user interface and a great flexibility to simulate an arbi-
trary SC filter topology, specially but not only, dedicated to
CAMs. However, there is a minor CPU-time penalty due to the
SIMULINK interface. For instance, a 65536-point simulation of
the modulator in Fig.3(c) including the most complex models for
building blocks takes 2 seconds using ASIDES and 5 seconds us-
ing the CAM-block library. This CPU-time increases up to 415
seconds if M-file building blocks are used - which means about 2
orders of magnitude slower than the approach in this paper.
As an illustration, Fig.6 shows the performance degradation of the
2-I2mb modulator in Fig.3(c) caused by two error mechanisms:
example
0 -
.
.
-50
8
.z 2 -loo
.z -150
-200
-250
m -
-‘“I (1 23
0 24
Frequency I Sampling Frequency
(1.25
I 1 26
0 27
Figure 5. Effect of non-linear settling on SI BP-CAMS.
.
A
-
.
IO
io3
IO
10
IO’
-300 4 -
Figure 6. Degradation of an SC 2-1 2mb XAM with INL and A ,
lo’
Frcq:c”cy
(Hz)
.
the Integral Non-Linearity (INL ) of the 3-bit DAC and the finite
DC gain of the opamps, A ,
. Both the isolated and the combined
effects of these two error mechanisms on the output spectrum are
shown in Fig. 6 when the modulator is clocked at fs = 35.2MHz
for INL = 0.1 LSB and A , = 50dB. In this case, as the INL
error is shaped by the filtering performed by previous stages, the
main degradation is caused by A v , basically increasing the quan-
tization noise power in the signal band.
CONCLUSIONS
A complete SIMULINK block library intended for fast and inter-
active simulation of SC, SI and CT ZAMs has been described. The
behavioural models of building blocks, including main circuit par-
asitics, have been incorporated as SIMULINK C-coded S-func-
tions. The combination of high accuracy, short CPU-time and in-
teroperability of different circuit models, make the block-library
into a valuable instrument to optimize the design of ZA ana-
log-to-digital converters using MATLAB.
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