Conference Proceeding

A New Low Power High Performance Flip-Flop

Department of Electrical and Computer Engineering, University of California, Davis, CA, U.S.A.
Midwest Symposium on Circuits and Systems 09/2006; 1:723 - 727. DOI:10.1109/MWSCAS.2006.382164 In proceeding of: Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on, Volume: 1
Source: IEEE Xplore

ABSTRACT Low power flip-flops are crucial for the design of low-power digital systems. In this paper we delve into the details of flip-flop design and optimization for low power. We compare the lowest power flip-flops reported in the literature and introduce a new flip-flop that competes with them.

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    ABSTRACT: Synchronous logic design is the dominant main stream integrated circuit design methodology. Flip-flops are an inherent building block in any synchronous design. Furthermore flip-flops constitute most of the load on the clock distribution and power networks, which are the main power consuming networks of a synchronous integrated circuit. We survey, design and simulate a superset of flip-flops designed for low power and high performance. We highlight the basic design features of these flip-flops and evaluate them based on timing characteristics, power consumption, and other metrics. Moreover, we propose a new flip-flop design. We go in depth into a finer granularity comparison of the lowest peak power surveyed flip-flops reported in the literature; we show the competitiveness of the new design and make our recommendations.
    IACSIT International Journal of Engineering and Technology. 06/2011; http://www.ijetch.org/papers/238-T634.pdf(Vol.3, No.3).

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Sep 17, 2012